# Soft Latch ON-OFF with support of DC High Voltage side, compatibile with Arduino or any Low Voltage MCU (with schematic)

## First Schematic

I'm trying to implement this schematic that I found in this interesting article (Soft Latching Power Circuits). This is a circuit can substitute a mechanical on off switch, and use instead a eletronic switch (transistor). It can be controllable by an MCU GPIO or via a simple momentary push button. The problem is how to manage an high voltage input:

I need an high voltage input and I'm not sure if al the component in this circuit is capable of like 30v or 60v. In particular:

• the Q1 Vgs is equal to vin? (in this case 30v but can be 40 60 ecc)
• the voltage on the switch is also equal to vin (30v)?
• I'm pretty sure that Q1 Vds is 30v...
• The Q2 Vgs is 5V in this case?

If the Q1 Vgs is 30v is pretty difficult to find a p-mosfet with that high voltage support? Because it's easy instead to find a very high Vds Voltage but not sure if good idea for vgs...

## Second Circuit

A little variant more complex it can be this:

Here there is two zener diode for logic and "protecting" the mcu. In the end of the article the author explain that the D2 protect the MCU for higer voltage. So I ask

• The D2 Voltage breakdown max had to be > 30V or equal?
• The D1 Voltage forward need to support 30V or could be less?
• In this case the Voltage on the switch is 5V or 30V? (I think 30v because the latch can not be activate otherwise...)

I also try to search here and I found this post Another latch on off circuit. That is a different circuit, but hacktastical answer: "for 60V you need voltage dividers to limit the (Q1 in this case?) FET gate-source voltages". So:

• Is it true? How to implement that voltage divider?
• A voltage divider can create a leakage of current in the off state? This could be make unusefull the purpouse of the latch itself
• And Finally all the passive component had to be support at least 30v is it correct?

Sorry for this many question and I hope I could explain well my problem! Thanks!

EDIT 27/04:

## Try to understand the comment made by Arthur Chassande:

You mean something like this? Using the breakdown property? of zener to protect the Q1?

• Z1 or Z2? Based on the answer of Fred Cailloux is not very clear now...
• The R1 is the limiting resistor? or need more resistors?

## Try to understand the answer made by Fred Cailloux:

It's an intresting thinking. So with the avalance effect of the Zener the voltage become stable. But probably I don't understand well the Zener function. Put it reverse in series with the Vin can stabilize tension but how can it help with high voltage? Maybe help with some spike like a filter?

• But is the Q1 Vgs still 30V?
• Also is there some loss and heat from the zener at high voltage?

Yes I do some reserch also on the regulator and I see that the LDO (Linear and Low Dropout regulator) simply can't manage 30V -> 5V o 3.3V ... I see some switching dc-dc step down converter that can (in theory). I understand maybe for high power circuit is not ideal, but it can be high voltage and low current if the conversion is efficent. I fear that this schematic lack of some type of protection for the MCU. I was thinking about optocopuler for the GPIO but this logic probably it can't work, without the power side of the MCU 5v.

EDIT 28/04

## Try to understand the answer made by Arseny Krasnov:

I think this is, for now, the most complete answer to my post. You answer all of my question :-) and simulate a schematic! Anyway i think the R1-R2 Divider is now more clear. However:

I repost your schematic for clarity here without simulation thing:

• Why you move the C1 after the Q1? I think that the C1 is like a filter for stop the latch to start itself randomly, when some voltage spikes happened. Is this function the same if I put after Q1?
• Why you remove the R2 pull down(?) from the gate of Q2?

The D2 Voltage breakdown max had to be > 30V or equal? - yes

D1 forward voltage will be around 0.6V for 4148 or less for Shottky.

Still not clear: so the important value here is the Reserve breakdown voltage of D2, for protect the GPIO pin. In your simulation 60V minimum right? And D1 not really a problem? Maybe the current? but I think is few milliamp in this case...

Leakage current in Q2 will be in any case, leakage in Q1 gate will be lower for lower voltage after divider

Still not understand the leakage. The Q2 when open still isolating ground so no leak should happend... Or for what i understand: when the latch is in OFF state, the Q1 is open because there is 30V (10V with divider) on Q1 Vgs. So we talk about a leakage of few micro ampere? with or without divider?

All transistors and diodes should be rated for maximum input voltage. I don't think it is a big problem for 60V and moderate current, there are a lot of cheap parts for this voltage.

I still have some doubt of missing some protection for the MCU and in general the low voltage side... However probably, like what you said choosing the right component, the Vreg and the isolation provide by the mosfet is sufficent...

• For both circuits you can protect Vgs of the PMOS transistor using a Zener diode (between gate and source) as well as a current limiting resistor on Q1's base. Choose Zener voltage below Vgs_max, and choose series resistance to limit power dissipation into Zener : Pzener = Vz * Iz, Iz = (Vin - Vz)/R Commented Apr 26, 2022 at 17:42

## 2 Answers

Here is the variant with voltage divider for p-mos gate voltage:

In this case Vgs maximum will be 60V * 20k / 120k = 10 V.

All transistors and diodes should be rated for maximum input voltage. I don't think it is a big problem for 60V and moderate current, there are a lot of cheap parts for this voltage.

Answers to other questions:

First circuit:

Q1 Vgs is equal to vin?

Yes

the voltage on the switch is also equal to vin?

Yes

I'm pretty sure that Q1 Vds is 30v...

Yes

The Q2 Vgs is 5V in this case?

It depends on MCU IO voltage. You should use transistor with low gate threshold voltage to drive it from MCU

Second circuit:

D1 and D2 are Shottky diodes in this circuit, not zeners. But you could use standard diodes also.

The D2 Voltage breakdown max had to be > 30V or equal?

Yes

The D1 Voltage forward need to support 30V or could be less?

Forward voltage will be around 0.6V for 4148 or less for Shottky.

In this case the Voltage on the switch is 5V or 30V? (I think 30v because the latch can not be activate otherwise...)

30V on the switch.

For 60V you need voltage dividers Is it true? How to implement that voltage divider?

see the answer beginning

A voltage divider can create a leakage of current in the off state? This could be make unusefull the purpouse of the latch itself

Leakage current in Q2 will be in any case, leakage in Q1 gate will be lower for lower voltage after divider

And Finally all the passive component had to be support at least 30v is it correct?

Not all. Gate-source resistors could be lower voltage.

Answers for new questions:

Q2 on your schematic is upside down. Q1 is also in wrong direction

Why you move the C1 after the Q1? I think that the C1 is like a filter for stop the latch to start itself randomly, when some voltage spikes happened. Is this function the same if I put after Q1?

Yes, some capacitor should be before Q1, right. I moved C1 just for simulation to add initial zero condition on output.

Why you remove the R2 pull down(?) from the gate of Q2?

It is not needed for simulation. But you are right, it should be in the real circuit to prevent some random turn on of Q2.

Still not clear: so the important value here is the Reserve breakdown voltage of D2, for protect the GPIO pin. In your simulation 60V minimum right? And D1 not really a problem? Maybe the current? but I think is few milliamp in this case...

All diodes should be rated for 60V minimum. Maximum current through D2 is 5V/1k = 5 mA and through D1 is 60V/120k = 0.5 mA for your schematic.

Earlier you asked about forward voltage - you could use diodes with any forward voltage < 1V. Diode forward voltage drop will be on GPIO_IN when switch is closed, it should be lower than MCU input threshold voltage for low logic level (Vcc/3 = 5V/3 = 1.7V for CMOS logic low).

Still not understand the leakage. The Q2 when open still isolating ground so no leak should happend... Or for what i understand: when the latch is in OFF state, the Q1 is open because there is 30V (10V with divider) on Q1 Vgs. So we talk about a leakage of few micro ampere? with or without divider?

Right, Q1 and Q2 are open but all things (except vacuum) have leakage current. For example Q2 2N7002 have 1 uA maximum leakage at 25C and 0.5 mA at high temperature: Q1 will have gate leakage current ~100 nA and drain-source leakage ~50 uA at 25C. Switch will have negligible leakage. The total leakage in your circuit will be the sum of these currents.

I still have some doubt of missing some protection for the MCU and in general the low voltage side... However probably, like what you said choosing the right component, the Vreg and the isolation provide by the mosfet is sufficent...

You could simulate or prototype this circuit, it is quite simple. If you need to comply some standards or expect noisy input voltage add and test some impulse overvoltage transient protection and maybe reverse polarity protection.

Try this with a Zener Diode. Choosing the correct voltage will adjust for your application. Just make sure that the Zener is of adequate power for your micro controller current requirement. Other consideration: make sure you do not power up the 5V regulator over the manufacturer specification sheet. Usually these regulators do not like more than 25 to 30 volts.

Obviously, that solution is not adequate for High Power circuitry. There are other solutions in such cases.