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enter image description here

My guess is PNP transistor might ensure fast turn off by shunting the gate capacitance (ie, when diode is reverse biased and the PNP is on.)

Additional questions:

  • Why is the gate current limiting resistance not present?
  • What is the role of R1 in Fig 2.7?

Ref: https://toshiba.semicon-storage.com/info/docget.jsp?did=59460

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4 Answers 4

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My guess is PNP transistor might ensure fast turn off by shunting the gate capacitance (ie, when diode is reverse biased and PNP is on)

That is correct.

Not sure why is the gate current limiting resistance not present?

It's not always needed. With a transformer drive, there will be significant resistance (a few ohms) in the transformer.

Also what is the role of R1 in Fig 2.7?

It's always a good idea to have a resistor that can discharge the gate especially with a transformer drive; if the drive becomes inactive (possibly due to transformer driver malfunction), something is needed to discharge any residual drain-to-gate currents that might inadvertently cause the MOSFET to start conducting.

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    \$\begingroup\$ I think the shunt resistor (R1) is just put in there out of habit. It serves a purpose on controllers which set the output Hi-Z when disabled/UVLO, but the secondary winding provides the leakage path here (+/- 1 diode drop) so doesn't matter. \$\endgroup\$ Apr 27 at 18:50
  • \$\begingroup\$ There is no explanation here for pulse rise /fall time nor pulse width with rising coil current after each pulse from start. R1 is redundant and has very little effect compared to the PNP. \$\endgroup\$ Apr 27 at 19:17
  • \$\begingroup\$ The parallel resistor serves no purpose. The transformer winding has <1kohm resistance all by itself. The are no “residual” currents other than those generated by stray magnetic fields picked up by the transformer – and are of no consequence. \$\endgroup\$ Apr 27 at 20:06
  • \$\begingroup\$ @Kubahasn'tforgottenMonica I mention the residual current from MOSFET drain to gate and I also mention malfunction in the transformer that may prevent any discharge path thus leading to possibly a catastrophic failure of the MOSFET and maybe some serious damage. \$\endgroup\$
    – Andy aka
    Apr 27 at 22:23
  • \$\begingroup\$ Wouldn't diode leakage prevent charging in the absence of pulses. The affirmations are void of an explanation \$\endgroup\$ Apr 28 at 1:36
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The other answers have covered the meat of the questions, however there is one more aspect to call attention to: the right circuit needs a resistor between transformer and base.

As shown, the C-B junction conducts when the winding goes negative. This occurs during flux reset. This diode drop is much lower than the diode+zener on the primary side, severely limiting the reset phase.

When a series resistor is used, notice it adds significant voltage drop when turning on; the B-E diode can be connected ahead of this resistor to solve this. It acts somewhat when turning off; effectively, the gate is driven low by this resistance divided by the BJT's hFE.

As for how useful this is, one must consider circuit impedances. Typical gate drive transformer designs have single layer windings or twisted pair construction. This gives modestly low leakage inductance, a characteristic impedance around 50-100 ohms. (Transformers, like transmission lines, have characteristic impedance and cutoff frequency; and like TLs, perform worse (less bandwidth, more attenuation) when operated at impedances far from there.) We need gate impedances typically under 20 ohms, so there will be some mismatch here. The effect is series inductance.

For analysis, we can simplify out the 1:1 transformer and get a series RLC loop, between driver (ideal voltage step source), resistance (including driver output resistance, winding DCR, any added resistance, and the internal gate resistance), inductance (leakage plus strays), and capacitance (use the average switching capacitance: Cg = Qg(tot) / Vgs(on)). We want an overdamped system, to avoid overshoot and ringing: R > sqrt(L/C). This will typically be limited by leakage, and so we cannot achieve very low gate impedances (much under 10 ohms, say).

So, with the series resistor added per above, if this is say 470Ω, and hFE is 100, the turn-off can end up with more like 4.7Ω, and very little inductance. Not a bad improvement over the 10-20Ω the bare transformer might get.

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    \$\begingroup\$ Yes Gate current needs to charge Ciss and discharge it with somewhat matched impedances but primary coil CCM will make this fail except for very narrow pulse d.f. applications. \$\endgroup\$ Apr 27 at 20:15
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The transformer load will never be sufficient to reset the primary coil even with R1 set to a 100 ohm value. R1 is redundant when the gate diode and PNP conduct the forward and negative voltage pulse.
enter image description here

It may be a few dozen or 100 pulses later but the FET pulse width will shrink to a few % due to the small di/dt relative to the continuous current mode (CCM) and lack of reset current below Zener voltage.

However, this design might be suitable where the desired d.f pulse is 1 to 3% max.

hmm oh oh

So I see a problem with this design in that the Zener cannot reset the full current drawn by the NPN and the residual current becomes the initial condition for the next pulse and it continuous to integrate. The Zener can only clamp the change in current after each input pulse but not quench it since there is no significant secondary load except gate capacitance and some insignificant R1 current. Therefore I respectfully say this design cannot work. It needs a push pull driver and AC coupled.

It turns out the datasheet already has that on the next page.

enter image description here

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To switch the FET on, its gate capacitance must be charged and to switch it off, that capacitance must be discharged.

Fig. 2.6

This uses series resistor R2 to limit the current drawn from the transformer or sunk by it when switching. R2 and the gate capacitance form an RC circuit, slowing the Vgs rise/fall times. R1 provides a transformer load as the FET gate is very high impedance. Together, R1 and R2 are a potential divider that can reduce the Vgs(max) as required.

Fig 2.7

This is trying to charge and discharge the gate capacitance as fast as possible. The series resistance is as low as possible, so no R2. R1 is a load resistance for the transformer output, in series with the diode.

When the transformer output is 0 V, PNP will be on. Vgs will be held to about 0.7 V, so FET is off. R1 allows the gate capacitance to discharge further towards zero so there is no residual Vgs.

When the transformer output rises, it would be clamped to about 1.4 V by the PNP being on and the drop of the forward-biased diode. However, before reaching 1.4 V the PNP base voltage will be off and Vgs can follow the transformer output voltage minus the 0.7 V diode drop.

When the transformer output falls towards zero, the PNP is turned on and Vgs is pulled down by the PNP to follow the transformer output voltage minus the 0.7 V PNP base-emitter drop.

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