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What is the correct way of estimating delays when doing operations in Verilog?

For example:

reg [31:0] a, b;
...
wire [31:0] res;
assing res = a + b;

The above + operator could lead to very different delays depending on if it is synthesized to a ripple-carry adder, a carry-look-ahead adder or a prefix adder.

How can I estimate the delay of that operation, so my simulations are closer to what the circuit will do in reality?

PD. Context

I'm designing a RISC-V processor in Verilog following a book. The book asks you to design different building blocks using logic gates, such as the adders mentioned above, shifters etc. In this case, one could estimate the delay of a logic gate (possibly oversize it) and implement all the required operators with gates, so the delay will be correct with regards to the estimation.

However, I have seen in the book's solutions to exercises that it uses a lot of operators (>>, +, -) directly without assigning delays. This will allow to test the design 'logic' is correct, but won't reveal anything about the maximum frequency allowed.

In addition, one cannot know what adder etc. the synthesizer will choose, so isn't it better to fix that from the beginning to test the design correctly?

Would it be valid to design an adder, calculate its delay and then assume that all the rest of the + operations will have this delay (maybe oversize it), instead of instantiate the mentioned adder again and again?

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    \$\begingroup\$ When you synthesize it for a real FPGA, Vivado (or whatever you use) is able to simulate the actual FPGA with actual FPGA delays. \$\endgroup\$ Apr 28, 2022 at 12:50
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    \$\begingroup\$ And the delay can vary a lot depending on how the synthesis tool places the gates. It can move them around to try and meet the required timing. Sometimes you will find that a gate takes a certain amount of time, but if you say it needs to be faster, then it will. \$\endgroup\$ Apr 28, 2022 at 13:10

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Realistically commercial digital logic design treats "get logic correct" and "fix timing" as two entirely separate phases of work. It's even more extreme in ASIC design than FGPA, but as someone else has said the delay you get in FPGA can depend a lot on placement. You cannot realistically estimate delay without placement. Sizing tends to be less critical in FPGA as the LUTs tend to be "one size fits all" and the tooling inserts buffers for you as needed.

It may well be the case (and it would be fastest) that the tooling assigns your adder to a predefined "adder" block on the FPGA.

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  • \$\begingroup\$ Then what is the utility of the delays in Verilog? \$\endgroup\$
    – Martel
    Apr 28, 2022 at 14:45
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    \$\begingroup\$ @Martel HDL is used for both synthesis and simulation. While writing code for simulation you can specify the delays in the code. \$\endgroup\$
    – devnull
    Apr 28, 2022 at 14:48
  • \$\begingroup\$ @Martel delays in Verilog are essentially a work of fiction that you can write. Only delays that are the result of physically simulating a particular layout should be considered "real" \$\endgroup\$
    – pjc50
    Apr 28, 2022 at 15:02
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    \$\begingroup\$ I cannot overstate how much non-Verilog details matter for practical delay calculations. Small details can change a lot. Many layout tools will let you specify the "random seed", since initial clustering can change the results by 10-20% it's not uncommon to do a number of layout runs and pick the best. \$\endgroup\$
    – pjc50
    Apr 28, 2022 at 15:05

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