Why specify a maximum pulse width for reset pin?

Question

A colleague and I are working with the Analog Devices AD74413R ADC for 4-20 mA current loop communications. On pages 15 and 16 of the datasheet, timing characteristics are presented.

We encountered an unexpected specification, a maximum duration for reset pulse width, highlighted in green:

We've tested and determined that holding reset low for longer than the "maximum" of 1 ms still facilitates a reset. Despite both the table and figure being labeled as "SPI Timing," I can't think of a reason that the reset functionality is lumped in with SPI timing.

Is the specification of a maximum pulse width for reset some sort of errata, or is there a use case we are overlooking?

Answer 1

When enabled the RESET button on the EVAL board simply grounds the /RESET pin (schematic available at the manufacturer's website). I see no specific instruction to limit the time of your finger on the button to less than 1 millisecond. This implies it's not much of an issue, at least in an office environment and with no strong requirements for reliability.

However, I would be loath to violate this requirement without definitive information from the manufacturer.

One possible reason for the requirement is that they don't want you to leave the inputs floating for an (undefined) "extended (period of) time". Rev 0 of the datasheet contains this:

If a channel is held in high impedance for an extended time, such as when the channel is not in use, it is recommended to enable the 200 kΩ resistor to ground. Enable the 200 kΩ resistor by setting the CH_200K_TO_GND bit in the ADC_ CONFIGx registers.

Obviously you can't enable the resistor whilst it's in reset (which makes the inputs high impedance).

Answer 2

My guess--and I don't think anyone could do any better than a guess--is that something inside (at least one silicon revision of) the ADC uses dynamic logic. Dynamic logic is like dynamic RAM; it has some cost and performance advantages, at the expense of needing to be refreshed regularly or it loses its state. This is why, for instance, some processors (including the original 6502; this isn't a new thing) have a minimum clock speed in addition to a maximum.

In dynamic logic, this refresh is provided by the clock itself, and perhaps other bits of normally operating logic as well. But when the chip is held in reset, it's possible that that interferes with the ability to refresh the dynamic logic, so it may lose its state over time. Perhaps the reset gates off the clock (if external) or stops the oscillator (if internal).

The actual time it takes for dynamic logic to lose its state is, like DRAM, highly variable. It depends on leakages which are not well controlled (beyond keeping them below a maximum limit) and vary by orders of magnitude over temperature. It's possible that 1 ms may be too long for worst-case parts at 105 °C, but a normal part at 25 °C could hold state for several seconds--I couldn't say.

I'll reiterate: this is just a guess. I don't know if it's possible to know for sure why there's a maximum without talking to the people at Analog, and they might not want to tell. But it seems like a logical guess to me.

Answer 3

I also asked this question of our FAE and received this reply:

Consideration of maximum time is useful once power-up time after reset is critical for your application.

A significant portion of power-up time (specified in datasheet = 10 ms) is taken by the charge pump itself.

Following the maximum guideline for the reset, decreases the charge pump power-up time.

Thus, it appears this is an important characteristic if you are trying to achieve minimum start-up time after reset.