My guess--and I don't think anyone could do any better than a guess--is that something inside (at least one silicon revision of) the ADC uses dynamic logic. Dynamic logic is like dynamic RAM; it has some cost and performance advantages, at the expense of needing to be refreshed regularly or it loses its state. This is why, for instance, some processors (including the original 6502; this isn't a new thing) have a minimum clock speed in addition to a maximum.
In dynamic logic, this refresh is provided by the clock itself, and perhaps other bits of normally operating logic as well. But when the chip is held in reset, it's possible that that interferes with the ability to refresh the dynamic logic, so it may lose its state over time. Perhaps the reset gates off the clock (if external) or stops the oscillator (if internal).
The actual time it takes for dynamic logic to lose its state is, like DRAM, highly variable. It depends on leakages which are not well controlled (beyond keeping them below a maximum limit) and vary by orders of magnitude over temperature. It's possible that 1 ms may be too long for worst-case parts at 105 °C, but a normal part at 25 °C could hold state for several seconds--I couldn't say.
I'll reiterate: this is just a guess. I don't know if it's possible to know for sure why there's a maximum without talking to the people at Analog, and they might not want to tell. But it seems like a logical guess to me.