# Op-Amp with current source input

In this op-amp circuit, the output is defined as $$\v_o = - i_sR\$$.

## Question 1

I am slightly confused about how the current flows in this circuit. By the principle of virtual ground, the inverting input is at 0V. The output is at some negative voltage. Hence the current flows from the current source, into the 0V virtual ground, through R and to the negative Vo. Now, at this point - if I consider that the ideal op-amp output stage is just a VCVS with no resistance, then this current should be absorbed into the VCVS source, correct?

## Question 2

If I put a resistive load to GND at the output

Will all of the $$\i_s\$$ current now flow through the load resistor? Or will the VCVS still absorb some current? I am having difficulty understanding that. I understand the VCVS is kind of setting the $$\V_{out}\$$, but I also know that voltage sources can absorb power. In the first case, the VCVS was taking all the current and absorbing the power, how come that will not happen here?

## Question 3

Considering the same circuit with the load resistor at the output. Is the output voltage now defined by $$\v_o = -i_ss*(R || R_L)\$$? $$\R\$$ is connected between virtual ground and $$\v_o\$$. $$\R_L\$$ is connected between real ground and $$\v_o\$$. Does that mean they are in parallel?

• Q1, Yes, you are right. Q2 You need to apply KCL. Notice the Vo will be negative thus, VCVS will now absorb IL and IS current. Q3. No, the output voltage will be equal to $v_o = - I_s*R$
– G36
May 1 at 17:56

if I consider that the ideal op-amp output stage is just a VCVS with no resistance

It means that this ideal model will be capable to provide any current, in any direction (sink or source).

The output voltage is defined by the negative feedback. In the ideal opamp, with no current at the inputs, all the input current goes through the feedback resistor. The output voltage will be whatever necessary to cause the current and keep the inverting pin at 0V.

If you connect the load resistor, this does not change the output voltage of the ideal opamp. So, the additional current for the output resistor must also be provided by the output, which is not a problem for an ideal VCVS.

• Thank you, this cleared it for me! Your answer and 'Math Keeps me Busy''s one have cleared up my doubts together. May 1 at 18:13

if I consider that the ideal op-amp output stage is just a VCVS with no resistance, then this current should be absorbed into the VCVS source, correct?

If there is no load on the op-amp, then all of the current through $$\R\$$ will be absorbed by the op-amp's output pin.

Will all of the is current now flow through the load resistor? Or will the VCVS still absorb some current?

Yes, current will still be absorbed by the op-amp. If I have done my math correctly, the current absorbed by the op-amp output pin will be

$$i_{out} = -i_s - \frac{i_sR}{R_L} = -i_s \left(1+\frac{R}{R_L}\right)$$

where $$\R_L\$$ in this case is the total load on the op-amp.

Does that mean they are in parallel?

No. Virtual ground is not ground. You can see this by connecting virtual ground to real ground. What would happen? First, all of the current from $$\i_s\$$ would go directly to ground, and not through $$\R\$$. Second, since the two inputs to the op-amp would have exactly the same input voltage, the output would be the input-offset voltage times the open loop voltage gain, (assuming the op-amp stays in the linear region). $$v_o = v_{offset}*A_o$$ Since connecting virtual ground and real ground will change the behavior of the circuit, a resistor with one end connected to virtual ground and another resistor with one end connected to real ground, cannot be in parallel.

• Thanks for the great response. May 1 at 18:09
• @alayoiskgfbfqhxjiw I added a formula to my answer for the current absorbed by the op-amp output pin. Didn't think about it too hard, but I think it is correct. May 1 at 18:17
• Sure looks like parallel loads in the linear operation as you say is not a problem, yet you contradicted that in comment to me. -1 Try to prove that the currents are not parallel in normal operation when they are virtually in parallel. That is like saying the virtual ground explanation is false and you ignore that it is true. May 1 at 19:04
• I've already explained. If you connect the ends of the resistances which respectively go to ground, and to virtual ground, together, you will change the behavior of the circuit. Therefore, the two resistances cannot be in parallel. May 1 at 19:14
• If connecting two nodes together changes the behavior of a circuit, then those nodes are distinct. If two resistors are connected to one common node, but each resistor is also connected to a distinct other node, then the resistors are not in parallel. I will not debate this further. May 1 at 19:33

KVL, KCL applies here Just assume this ideal OP Amp has null input current but forces the output to also null the differential input voltage. Then the current path becomes obvious. This can only occur if the output is inside the linear range, otherwise, the gain becomes zero if saturated to either supply rail OK?

Yes the feedback voltage and load voltage is from the same node so the "loads are in parallel". Both also are shown to use 0V or ground as a reference, but that is your choice.

• The feedback resistor and the load resistance are not in parallel. Downvoted May 1 at 18:01
• They are "virtually" in parallel and Iout feeds both currents to 0V. So for the ideal Op Amp, yes they are in parallel. @MathKeepsMeBusy Show me the math that proves otherwise if you think you are correct.. May 1 at 18:20
• Try an experiment. Short the virtual ground with the real ground. Does it change the behavior? yes it does. May 1 at 18:21
• Yes it violates the linear operation zero * infinity May 1 at 18:23
• And does the output depend upon the current source any more? May 1 at 18:28