I’m trying to implement this boolean function using CMOS transmission gate in LTspice.

F = AB + A'C' + AB'C

I've used two symbols in my project:

  1. Transmission gate symbol schematic:

enter image description here

  1. 180nm CMOS inverter symbol (PMOS L=180nm and W=720nm)(NMOS L&W=180nm):

enter image description here

This is my circuit for the boolean function:

enter image description here

This is my simulation for the above circuit:

enter image description here

As you can see, the output of the boolean expression is correct, but there are some unwanted spikes and falls.

How can I remove them?

I checked for spikes in AB, A'C', and AB' and it turns out they too have some small spikes which contribute to spikes in the final output. Is it just a transmission gate thing?

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    \$\begingroup\$ Classic issue. Have you tried with some very high resistance to ground on “problematic” nodes, say a megaohm? Real models instead on default ones? Tiny RC snubbers across your semiconductors? Alternate solver instead on the default one? \$\endgroup\$
    – winny
    Commented May 2, 2022 at 9:29
  • \$\begingroup\$ I'm not exactly sure how i should do that. Where exactly am i supposed to connect a very high resistance? Same for RC snubbers, where exactly am i supposed to connect that? Sorry I'm still sort of new to all this so I'm not sure about all these terms. \$\endgroup\$
    – Ben Paul
    Commented May 2, 2022 at 10:38
  • 1
    \$\begingroup\$ Just put a 1Meg resistor from every switched circuit node to ground. \$\endgroup\$ Commented May 2, 2022 at 11:49
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    \$\begingroup\$ @winny are you sure this is THAT type of voltage spike? I don't think so. \$\endgroup\$ Commented May 2, 2022 at 12:13
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    \$\begingroup\$ AFAIK this would be called a "glitch" in digital logic terms and is an expected result of complex combinational circuits. That's why sequential elements are used that only act on clock pulses, and the clock pulses are spaced apart far enough to let the combinational elements settle before the next pulse. \$\endgroup\$ Commented May 2, 2022 at 12:14

1 Answer 1


Add some D Flip Flop to your output of your circuit. Clock the FF circuits just slower than the rate of your glitch. Normally logic circuits have glitches due to different delay times through logic circuits, but not in your case. You have rise/fall time issues which can be resolved by using flip flops.

  • \$\begingroup\$ Alright ill try this and let you know. D flipflop has input (D) and two outputs right (Q and Q')? How exactly would i connect the outputs of the d flip flop? Do i join them and measure or do i just leave them as it is and measure the output of my circuit as usual? I've never really used d flip flop in combination with other circuits before, so that's why I'm asking. \$\endgroup\$
    – Ben Paul
    Commented May 2, 2022 at 13:41
  • \$\begingroup\$ Thankyou so much. This worked. I just inputed clock with the same pulse rate as input A. And gave the output as D. Taking the output from Q gave me an output free of errors. \$\endgroup\$
    – Ben Paul
    Commented May 2, 2022 at 15:35
  • \$\begingroup\$ Awesome! Can you accept my answer, I'm a new user and need the community cred. \$\endgroup\$ Commented May 2, 2022 at 18:40

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