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Is there a difference between these two SystemVerilog function declarations? Does the "input" keyword change any functionality? I've seen it both ways in examples.

function int addition (input int a, b);
  return a + b;
endfunction

function int addition (int a, b);
  return a + b;
endfunction
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1 Answer 1

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There is no difference between the two functions. In your code, the input keyword is optional. Refer to IEEE Std 1800-2017, section 13.4 Functions:

Function declarations default to the formal direction input if no direction has been specified. Once a direction is given, subsequent formals default to the same direction.

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