Hello, I am doing digital electronics and I have never seen this notation 5o define a function. Can someone explain me with details what happens when CLK is 1 please
Thank you
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.
Sign up to join this communityHello, I am doing digital electronics and I have never seen this notation 5o define a function. Can someone explain me with details what happens when CLK is 1 please
Thank you
Looking at that PMOS in the middle top, with f(a,b,c) at its gate, I'm guessing that device doesn't have the same drive as the others, and functions as a "weak holder" ensuring that once driven high, that "center node" driving the output pair, it will stay high keeping the output low.
It's set high by the negative clock pulse. The positive clock pulse activates the bottom NMOS, giving it the opportunity to be driven low through your a, b, and c input transistors. If it's not driven through those, it remains high, and the output remains low.
In order to set the center node low and the output high, at least one of those branches will need to conduct. Figuring out what conditions make those conduct (one or both) will reveal the logic function.