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I have implemented an asynchronous FIFO

However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees.

Both read_clk and write_clk are having the same clock frequency.

Could anyone advise ?

Please see below the reports from Vivado tool:

timing

schematics

report_cdc

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  • \$\begingroup\$ Why a do you use phase shift? Why a fifo? \$\endgroup\$
    – gotchi85
    May 3 at 19:06

1 Answer 1

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Let's consider that your clock is a 100 MHz one. The period is 10 ns.

Read clock has a phase shift of 270 degrees which corresponds to 7.5 ns.

Write clock has a phase shift of 90 degrees which corresponds to 2.5 ns.

The time difference between your two clocks is 5 ns. It is 200 MHz.

So depending on the clock frequency and shift, the constraint can be stronger (200 MHz) in my example

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  • \$\begingroup\$ I had added some Vivado reports outputs in my original question. Someone told me to use set_max_delay , but I am not sure how and which path to use it on. Should I use set_max_delay between read_pointer and write_pointer ? \$\endgroup\$
    – kevin
    May 4 at 1:12
  • \$\begingroup\$ Are your two clocks coming from the same oscillator? If it is not the case, yes you should put a set max delay \$\endgroup\$
    – gotchi85
    May 5 at 12:22

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