Firstly, yes I contacted ST for answers. Until now, no answer.
I'm using STM32F429 MCU and embedded USB FS PHY. To keep the 48 MHz USB PHY clock the maximum PLL clock that I can achieve is 168 MHz, unless the VCO clock is increased to 720 MHz. Then, I can achieve the PLL maximum frequency of 180 MHz and also provide the 48 MHz clock.
The datasheet says that the VCO clock should be on an interval of 100 to 432 MHz. Nevertheless, the same datasheet says that those conditions (100~432MHz) are valid for a source voltage of 1.7 to 3.3V.
Once my application always works at 3.3V, I've made some tests with VCO Clock at 720 MHz and everything worked!
Now, my questions are:
- Is it safe?
- Which tests should I run to verify the safety of this approach?
No, it's not a hobby project. In fact, I'm trying to make some low-level performance improvements once the opcode has grown bigger and bigger since the first market release. Today it has 1.8 MB.
Anyone who has worked on a long-term project that has hundreds of thousands of lines of code knows that there are a lot of 'truths' or myths that are not entirely true. So, it's a good thing to question those from time to time.
By design, if a VCO can operate within a range of frequencies with a power source of X watts, it surely can operate in a bigger range with a power source of X + Y watts. Of course, components' saturations, and resonations must not be reached. How much? I do not know. Hopefully, ST experts know.
If ST would put into the datasheet all the information gathered during MCU design and rehearsal it would be unreadable. But, only because some information is not in the datasheet it not means that the information does not exist or it could not be true.
We are not mad to release something that still unclear, without all necessary tests.
Finally, I know that I'm going on an unknown path, that is the reason that I've come here. To hear some wise words from someone that has done something similar.