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I am new to LTSpice and I am trying to simulate an RLC parallel circuit with a DC source. The ideal switch is initially open and then closed at t=0+. The input is an ideal DC source with 1V. I have a couple of questions.

  1. Is my output voltage V0 correct, going to from 0V to 1V and then exponentially decreasing?
  2. Why does the voltage V0 only reach 500mV when a 1Ω resistor is used and hit 1V when a 1kΩ is used?

Circuit schematic 1 Circuit schematic 2

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  • \$\begingroup\$ With an empty MYSW SW(), you're accepting LTSPICE's default internal switch resistance - do you expect it to be zero ohms? \$\endgroup\$
    – glen_geek
    Commented May 4, 2022 at 0:53
  • \$\begingroup\$ Yes, I wanted to model an ideal switch. \$\endgroup\$
    – RSH
    Commented May 4, 2022 at 0:56
  • \$\begingroup\$ Default is one ohm. I'd suggest not forcing zero - you may run into convergence problems... perhaps MYSW SW(Ron=0.001 Roff=1e6 Vt=0.5) \$\endgroup\$
    – glen_geek
    Commented May 4, 2022 at 1:21
  • \$\begingroup\$ When I used (Ron=0.001 Roff=1e6 Vt=0.5), V0 goes from 1V to 0.5V exponentially and takes almost 3s to settle down. \$\endgroup\$
    – RSH
    Commented May 4, 2022 at 1:40
  • \$\begingroup\$ Why don't you apply Linear Superposition principles for each element? and look at T=RC and T=L/R and V/Rsw = I surge , then Q=Zo/R , \$Zo=\sqrt{\frac{L}{C}}\$, I(C)=CdV/dt and V{L}=LdI/dt \$\endgroup\$
    – D.A.S.
    Commented May 4, 2022 at 6:53

1 Answer 1

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Ignoring the resistor and inductor, you've got a capacitor connected directly across a voltage source, so it will fill up very quickly. Then, the current through the inductor L1 will increase since it has voltage across it. Higher current through the inductor will cause higher current through the switch. Since the switch is modeled with a non-zero on-resistance, you'll get a voltage drop across the switch. As the switch current increases, the switch's voltage drop increases (V_switch_drop = I_switch * R_switch), until the switch voltage drop is equal to the input voltage (1V). This causes the gradual ramp to 0V on the switch output node. So,

  1. yes, your simulation is working properly, though it's sort of an odd circuit to model. A real-world circuit may act differently due to parasitic resistances and such in the components.
  2. The switch resistance and R1 form a voltage divider at the beginning, and the capacitor fills up to that voltage at the start. If the switch resistance defaults to 1 ohms as glen said, then when R1 is 1 ohm, R_switch and R1 make a 1/2 divider, so C1 fills to Vin/2 = 0.5 V. When R1 is 1k ohm, R_switch and R1 make a 1000/1001 voltage divider, so C1 fills to 0.999 V (essentially 1V).
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