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As of this moment, does anybody make a single-chip flip-flop that latches its state on BOTH the falling AND rising edges of a clock? In other words, instead of latching an input's state and setting its output's state to match ONLY when a clock transitions from high to low, do it once when the clock transitions from high to low, do it again when the clock transitions from low to high, and repeat?

Put another way, imagine that I have a square wave generated by a Si5351 with a frequency that's somewhere between 3.5 MHz and 30 MHz (maybe 18 or 21, if push came to shove and achieving 30 made things too difficult). I want to latch it through a flip-flop so its timing is determined by the Si5351's square wave, and the input itself is the same square wave, so the output basically consists of the input plus whatever delay is imposed by the chip itself.

Background:

I'm building a class E ham transmitter (3.5 MHz to 18/21/30 MHz), and want to give it BPSK capabilities as well. The idea I came up with is to use one of the Arduino's pins to indicate phase (Si5351's square wave and phase pin are inputs to a 74LVC86 XOR gate), so the phase pin can selectively invert the Si5351's square wave when necessary to flip the phase.

The catch is I need to synchronize those phase changes to the square wave itself to avoid spectrally-messy output (so a phase change occurs by extending the Si5351 square wave's current high or low by a half-cycle).

My first idea was to insert a flip-flop between the Arduino's phasePin and the XOR gate's input, so changes to phasePin only propagate together with the falling edge of the Si5351-generated square wave. The catch is, fast logic chips are fast, but they're still not instantaneous, and I'd still end up with a glitch of a few nanoseconds.

My second idea was to delay both the Si5351's square wave and the phasePin by the same amount by latching both through flip-flops. The catch is now triggering a latch on the Si5351's falling edge won't work, because the square wave's latching is timed to itself & will therefore always see the same state at "latch time".

Ergo, the double-pumped idea. If the latch updates on the falling AND rising edges, everything works perfectly. The Si5351's square wave gets delayed slightly by the flip flop, the phasePin's value gets delayed by the same amount by an identical flip flop, and both end up coming together at the XOR gate's inputs more or less simultaneously.

I contemplated the use of a Schmitt gate to smooth out the momentary glitch, but I'm pretty sure that would cause more problems than it would solve, by mangling ALL of my low-high transitions for the sake of cleaning up a relatively rare phase transition.

I suppose my next-best option would be to use the Si5351's second clock at double the first's frequency to drive the latches and in fact, that's what I'd do if there's no such thing as a presently-existing chip with double-pumped timing logic, but if such chips DO presently exist, using one would be my preferred solution, because it would leave the other clock output available for future uses.

So, do logic gates with "double-pumped" timing exist as something you can buy today?

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    \$\begingroup\$ Can you accept a latch which gets its enable from a state transition detector? Or as well a D-flipflop which gets its clock from a state transition detector? State transition detector = exclusive or between a pulse and it's delayed copy. \$\endgroup\$
    – user136077
    May 4, 2022 at 18:18
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    \$\begingroup\$ It doesn't fit your question, but the answer to your problem is probably to generate twice your desired frequency all the time, then feed that to a "toggle flip flop with hiccup" -- i.e., make a state machine that normally just toggles (divide by two), but on the rising or falling edge of some asynchronous signal it will hold state for one clock, thus switching phase. You'll need at least three flip flops, and maybe more if you're worried about the "hiccup" input causing problems with setup or hold times because you're crossing a clock boundary. So -- minimum of two 74AHC76 chips. \$\endgroup\$
    – TimWescott
    May 4, 2022 at 18:40
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    \$\begingroup\$ Most FPGAs have DDR flipflop options on their I/O pins. Whether that can be utilised in any way for your project I have no idea. \$\endgroup\$
    – user16324
    May 4, 2022 at 19:11
  • \$\begingroup\$ Sounds like DDR. \$\endgroup\$
    – winny
    May 5, 2022 at 9:18

1 Answer 1

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As @TimWescott proposed, first idea ...

Do you need something as this?enter image description here

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