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Why is multiplication with a fixed coefficient cheaper in ASIC as compared to variable multiplication?

Would it be faster using an FPGA inferring a DSP Slice?

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  • \$\begingroup\$ A register is more expensive than ROM \$\endgroup\$
    – DKNguyen
    May 5, 2022 at 0:28
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    \$\begingroup\$ Besides saving the register, if you know the coefficient in advance you can omit logic anywhere there is a zero bit. With a DSP slice your optimization will be more limited since your hardware is fixed. \$\endgroup\$ May 5, 2022 at 1:18

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A multiplier in an ASIC is often implemented as many layers or a tree of carry save adders, one CSA layer per each possible "1" bit in the multiplier. If the multiplier can be any value, the number of bits in it is more than for any constant multiplier other than all ones. So the number of CSA layers for the constant will be less.

Depending on how an FPGA fabric is implemented, a hard macro in an FPGA (with a custom transistor layout) containing a large number of CSAs can be smaller than a fewer number of routed CSAs implemented with FPGA cells or LUTs. And smaller logic with shorter routing will most often be faster.

And as stated in comments to the question, a constant might not require any register cells at all, unlike a variable multiplier value.

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