I'm using an FPGA to drive an ADC, let's say AD9226, 12-bit resolution, and 65 MSPS sample rate. I can drive it with a 50 MHz clock - from my understanding, that will give me a 50 MSPS sample rate. Now I want to sample a 1 kHz sine wave with 512 samples in one period, which means I need a 5.12 MSPS sampling rate. My confusion is about how I can control the sampling rate of the ADC: do I have a 5.12 MSPS sampling rate if I give a the ADC a 5.12 MHz? What is the relationship between ADC sampling rate and ADC clock?

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    \$\begingroup\$ "What is the relationship between ADC sampling rate and ADC clock?" That information is always in the datasheet. "I can drive it with a 50 MHz clock, from my understanding, it will give me a 50 MSPS sample rate" So if that's your understanding, what's the problem with 5.12MSPS? So long as you do not go below the ADC's minimum frequency which should also be in the datasheet. \$\endgroup\$
    – DKNguyen
    May 6, 2022 at 3:46
  • \$\begingroup\$ Usually the ADC clock is the sample clock, or at least a factor of it. The datasheet of ADC will explain the relationship between clocks explicitly. \$\endgroup\$ May 6, 2022 at 4:12

1 Answer 1


In the AD9226 datasheet, Figure 1 at the bottom of page 3 shows you one output sample per clock. The sample rate is therefore the same as the clock rate.

In the switching characteristics table also on page 3, note 1 says the clock period can be extended up to 10 μs without degradation of specified performance. That means you can clock the device at any frequency between 100 kHz and 65 MHz.

Other ADCs might have a different relationship between clock frequency and sample rate, and would have a different minimum and maximum clock frequency range. The reason for the maximum is obvious. The minimum is there because you might have interstage charge transfers on small and leaky capacitors, which will only maintain their charge within specification for a certain time.

To get 512 samples at 1 kHz, you would need to run at 512 kHz, not 5.12 MHz.

Usually, you'll run an ADC like this at a constant rate, and use decimation filtering in the FPGA to achieve different sample rates. Then you gain the benefit of only one anti-alias filter design, and improved noise due to oversampling at lower sample rates.

There's a very efficient class of decimation filters called CIC (Cascaded Integrator Comb) or Hogenauer filters that are ideal for reducing the sample rate down by any integer ratio (not limited to 2n, as large as you like in a single block) from high frequency to about eight times the final frequency. If you're going to analyse the output with software, that's all you need. If you're going to use the output in real time, then you need some designed FIR filters to correct the frequency response while reducing the last factor of 8.


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