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I am working on a 7-level power micro-inverter which composed mainly by power MOSFETs. These logic-level MOSFETs (IRLZ24NS) are driven by separate photovoltaic gate drivers with integrated fast turn-off (Broadcom ACPL-K30T). The problem comes when I try to simulate the circuit and compare the results with those obtained by experiments. The circuit topology with relevant signals looks like this:

LTSpice Simulation

As you can see, the gate-to-source voltage of the MOSFET M11 (V(g)-V(s)) at time starting from 11.68ms should be near to zero volts and not 2.31V, because the charge of the parasitic capacitors (Cgd and Cgs) will be discharged through the gate driver circuitry. This assertion was verified by breadboarding and gives the following result:

Lab measurements

Noting that during my experiment I was using available Panasonic AVP1122 gate drivers instead of Broadcom ACPL-K30T which has comparative capabilities. However, I guess that problem comes from the ACPL-K30T SPICE model itself, I've tried to decipher it but didn't succeed, so I ask you SPICE gurus to help me understand the reasons behind this issue. The SPICE code is given below:

* ACPL-K30T  Spice Macromodel
.subckt ACPL-K30T AN CA VOUT- VOUT+
E1 N002 CA N014 N016 {CTR}
XX1 AN CA N016 N014 vbu
XX2 N002 CA N017 N015 pdnoc
XX3 N002 CA N008 N017 pdnoc
XX4 N002 CA N015 N013 pdnoc
XX5 N002 CA N013 N012 pdnoc
XX6 N002 CA N012 N010 pdnoc
XX7 N002 CA N010 N007 pdnoc
XX8 N002 CA N007 N004 pdnoc
XX9 N002 CA N004 N003 pdnoc
XX10 N002 CA N003 P001 pdnoc
XX11 N002 CA P002 P003 pdnoc
E2 N011 VOUT- N008 N001 1
R2 N009 N011 1k
D1 VOUT- N001 D
D2 N008 VOUT+ D
E3 N009 N006 N008 VOUT- 1
Q1 VOUT+ N006 N005 0 NPN
R3 VOUT- N005 3k
C1 VOUT- N009 37n
XX12 N002 CA P003 N001 pdnoc
XX13 N002 CA P001 P002 pdnoc
C2 VOUT- VOUT+ 100p
.param CTR=0.083
.ends ACPL-K30T

.subckt vbu AN CA LOPN LOPP
RSERIES AN 5 5
DELECT 5 CA VBUNOR
ELED 6 LOPN 5 CA 1
DOPTIC 6 8 VBUNORC
FPHOTO LOPN 3 VSENSE 1
VSENSE 8 LOPN 0
RL 3 LOPN 0.1
EOUT LOPP LOPN 3 LOPN 60
VSIM LOPN CA 0
Rnl 6 N001 5k
Vnl N002 LOPN 0
Fnl LOPN LOPN Vnl 1
Dsw N001 N002 DSW
.model DSW D Is=1e-4
.model VBUNOR D IS=330E-21 N=1.5 XTI=3 EG=1.52 BV=10.38 IBV=100u
+  CJO=60p VJ=.75 M=.3333 FC=.5 TT=20n
.model VBUNORC D IS=330E-21 N=1.5 XTI=3 EG=1.52 BV=10.38 IBV=100u
+  CJO=0 VJ=.75 M=.3333 FC=.5 TT=0
.ends vbu

.subckt pdnoc LOPP LOPN AN CA
D1 AN CA PDC
G1 CA AN LOPP LOPN 0.0010
.model PDC D IS=1E-14 N=1.5 CJO=0p M=0.95 VJ=0.75 ISR=100.0E-12 BV=100 TT=5E-9
.ends pdnoc


.model D D
.model NPN NPN
.model PNP PNP

EDIT: The IRLZ24NS SPICE model is also given

M1 9 7 8 8 MM L=100u W=100u
.MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=2.48862 LAMBDA=0.00533167 KP=29.3169
+CGSO=4.26728e-06 CGDO=2.65192e-07
RS 8 3 0.0611426
D1 3 1 MD
.MODEL MD D IS=1.80461e-10 RS=0.0124814 N=1.29036 BV=55
+IBV=0.00025 EG=1.2 XTI=3.10139 TT=1e-07
+CJO=3.29199e-10 VJ=1.14295 M=0.476565 FC=0.5
RDS 3 1 1e+07
RD 9 1 0.0001
RG 2 7 7.88523
D2 4 5 MD1
* Default values used in MD1:
*   RS=0 EG=1.11 XTI=3.0 TT=0
*   BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=4.16435e-10 VJ=0.5 M=0.641546 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
*   EG=1.11 XTI=3.0 TT=0 CJO=0
*   BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.400926 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 1.2203e-09
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
*   EG=1.11 XTI=3.0 TT=0 CJO=0
*   RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.400926
.ENDS IRLZ24NS
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  • \$\begingroup\$ If you want to share your schematic you need to ensure that all the 3rd party libraries and symbols are accessible. Currently, only the subcircuit for the ACPL is there; for the MOSFET it's missing (or the symbols). If you suspect the ACPL to be the problem, replace them with a VCVS, or a VCCS+R. If you suspect the transistors to be the cause, replace them with either some from the database, or VCSW(+antiparallel D). But I suspect the inverter schematic is not correctly drawn (pg. 5). \$\endgroup\$ Commented May 6, 2022 at 13:50
  • \$\begingroup\$ @aconcernedcitizen As requested I included the SPICE definition for the power MOSFET. However, the inverter schematic is correct and was validated experimentally. My suspect is that the gate driver model cannot control appropriately the MOSFET when it is in high-side mode, the drain-to-source voltage changes over time during the off-state and then charges the parasitic capacitors. \$\endgroup\$
    – settimed
    Commented May 6, 2022 at 15:17

1 Answer 1

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Your inverter schematic is unusual at best. It looks incorrect (or making assumptions that aren't apparent to me) at first glance, but I'm going to ignore it for now.

The gate driver you have chosen is nice for the simplicity it provides but it isn't good for inverter (or any sort of "fast" switching). The reasons are pretty simple and significant:

  • It sources very little current (10-15 µA with 20mA LED drive), meaning turn-on is very slow. This will lead to much greater power loss in the transistor than necessary.
  • The output voltage varies strongly with temperature (5-8 V over temperature, with the lowest voltage at the highest temperature, making your MOSFET RDSon even worse)
  • It does not actively clamp the gate voltage to 0V!

That last point is probably where you're finding an issue. My guess is that the model for the ACPL-K30T is pretty honest in that it doesn't actively short gate-source when off. The gate voltage is free to float up to the point that the internal SCR (Q3, Q4) turns back on.

ACPL-K30T Internal Schematic

I think you are seeing capacitive coupling of your drain voltage through to the gate in your simulation. The drain-source voltage change at the same time that the gate voltage changes is too strong of a coincidence for me to ignore.

Your oscilloscope may provide more than enough "leakage" with the high-impedance off state to give you the result you expect, especially if that's a floating node. If you're not using a 10x probe, then it looks like a place to start would be a 1 MΩ resistor across gate-source in your simulation.

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  • \$\begingroup\$ +1 to mention the impedance of oscilloscope probe. So as I understand the fact of not clamping the gate voltage to zero is a normal behavior of any gate driver. Is that correct? \$\endgroup\$
    – settimed
    Commented May 6, 2022 at 17:42
  • \$\begingroup\$ A "normal" gate driver drives the gate voltage to its VDD or VSS with a 1-100Ω (ish) source resistance, and the power supply is capable of delivering that current, whether it is an isolated supply or a bootstrap capacitor. \$\endgroup\$
    – W5VO
    Commented May 6, 2022 at 18:15
  • \$\begingroup\$ but what about a normal photovoltaic gate driver? \$\endgroup\$
    – settimed
    Commented May 6, 2022 at 18:47
  • \$\begingroup\$ A photovoltaic gate driver is not normal to me - I don't see (through my work/use) a lot of applications where one makes sense. I'm drawing a blank on how an effective ground clamp could be implemented with no voltage available, but be completely turned off with just 5V of signal... \$\endgroup\$
    – W5VO
    Commented May 6, 2022 at 20:16
  • \$\begingroup\$ What about the idea of puting a depletion-mode MOSFET at the output of the driver? \$\endgroup\$
    – settimed
    Commented May 6, 2022 at 20:36

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