Why do logic gates need multiple MOSFETs?

Question

I've just started learning about physics and electronics, and right now I'm learning about creating logic gates with CMOSFETs (Complementary MOSFETs). I'm interested in this because I'm a "high-level" programmer, meaning I write code using the C# language and draw advantage of the .NET Core framework, and I'd like to know how code gets executed at the "lowest" levels, so I can improve my skills. For now I'm ignoring the math and the correct terms, and just concentrating on the concepts, so please excuse my ignorance and terminology, or the lack thereof. Actually, I've gone so far as learning how BJTs and MOSFET's work/act with cations, anions, electrons, n-type and p-type doping, depletion zone and flow of electrons etc. Also I've looked into FINFET's and the latest MOSFET design/architecture with even more gates, the so called "nanosheet transistor".

For now I'm interested in learning why the very simple NOT gate (inverter) is designed with 2 CMOSFETs. Just conceptually, not the math of it (if that's possible). Why not just one PMOSFET (P-type MOSFET)? Like this...

My thought is, either there is no (or negative) input and therefore a high flow of electrons from the output (1), or there is an (positive) input and there is no (or very little) flow of electrons from the output (0). Either there is high voltage in a closed circuit or there (almost) isn't. I assume the output is connected to the gate of another CMOSFET, like in a semiconductor chip, so I'm not sure how the output would be floating.

I think there's something I'm not understanding... Every contribution and/or explanation is appreciated.

EDIT: This is what I've concluded after the discussions in the comments and reading hacktasticals answer.

Answer 1

The ‘C’ in ‘CMOS’ means ‘complementary’. CMOS uses both P and N FET types that work with opposite polarity.

A CMOS inverter (P source to +V, N source to GND) works much like a single pole double throw switch. With a high input, the n-FET is on, connecting GND to output. With low input, the p-FET is on, connecting +V to output.

(try it here.)

The neat trick with the CMOS inverter is that only one FET is on at a time, so +V is never connected directly to GND through the pair. So the only power used is in swinging the output high or low. This makes CMOS very power efficient compared to other technologies like NMOS (n-FETs with pull-up) or bipolar. This power advantage is why CMOS is the dominant logic technology today.

Now, there's a few more things to clear up.

• Current flow is positive to negative, electron flow is negative to positive.

Positive-to-negative flow is called conventional current. This understanding of current was adopted many decades before the discovery of electrons, so it persists today. Blame Ben Franklin.

We get into electron flow when we study things at the electron level, like semiconductor physics and vacuum tubes. Don't worry too much about it. The basic equations like Ohm's Law, Kirchhoff's Laws and Maxwell's equations still work just fine using conventional current.

I bring this up as it will matter when you study circuits, which by default use 'conventional' current notation.

• n-FETs turn on with +Vgs, p-FETs with -Vgs

The 'inverter' diagram you show would basically be useless. All that would happen when the p-FET gate is brought low is shorting +V to GND, possibly burning the FET in the process (the FET is also flipped: source should be to +V usually.)

You could flip the FET and insert a pull-down resistor between source and GND, then you'd have a PMOS inverter. Its N complement would have source to GND and a pull-up between +V and drain.

(Yes, I'm well aware FETs are bidirectional, a point I've made many times. Work with me here.)

• If you're interested in programming languages used in EE, consider learning Verilog and/or VHDL, and Spice

Verilog is the dominant language in VLSI design, while FPGA people seem to like VHDL. Verilog is C-like; VHDL is more like Ada, Pascal: it’s verbose, strongly typed and object-oriented. (Deeper dive here: VHDL vs. Verilog)

Spice is a circuit simulator, originally developed at UC Berkeley in the early 1970s. There are free versions of it available (LTSpice, Micro-cap, QUCS, etc.) for you to play with, as well as commercial tools like Pspice from Cadence.

This forum includes the CircuitLab sim, which while useful for making schematics it’s pretty limited. If you want accurate and free, use LTSpice; if you want quick-and-easy there are better choices…

… like Falstad. You’ve already seen it: I used a Falstad circuit sim above. Falstad circuit sim is based on Javascript, and sets itself apart from the traditional Spice flows (get it?) by being interactive and having some really neat visualization tools. It's platform neutral (runs in your browser) and reasonably fast, but it also isn’t as accurate as ‘real’ Spice.

Falstad also has a whole collection of simulators for electomagnetics, acoustics, mathematics and other physics-related stuff.

Answer 2

For now I'm ignoring the math and the correct terms, and just concentrating on the concepts...

The right sequence

Indeed, circuits (like everything else in life) are best understood in this sequence - first the concepts, then the specific implementations and the details around them. Concepts do not depend on the specific implementations (switches, relays, tubes, diodes, BJT, MOSFET, etc.); they are eternal and immortal - something like the human soul, while the implementations are like the human body.

It is a common mistake to explain the specific circuit implementation and not the basic idea on which it is built. So I will focus on the concepts because disclosing the basic circuit ideas is my favorite activity.

The concepts behind CMOS

Two electrical concepts (electrical analogies) can be used here to explain the basic idea behind CMOS - 3-pole (SPDT) switch and potentiometer. Let's follow the evolution of the CMOS idea..

The problem

Electrical circuits. Simply put, the output of a digital circuit (logic gate) switches the supply voltage between its two values ​​- Vcc and zero (ground). In household electrical circuits, automotive circuits and in general, this is done by a simple 2-pole switch connected in series between the power supply and the load. Typical examples are car ignition and starter switch.

This configuration works well there because, as a rule, electric loads have low resistance. So when the switch is off, the voltage on the load is zero as it should be.

Electronic circuits. Electronic (digital) MOS circuits have high input resistance. So, when cascaded, they act as high-resistance loads. In this case, when the humble 2-pole switch is off (the so-called "open collector" or "open source"), the voltage at the next input will be undefined since it will be affected by various disturbances (e.g. leakegas).

Another problem is the charged input capacitance that cannot find a path to discharge.

There will be a problem also if the load is connected not to ground but to Vcc or to another point having a voltage between zero and Vcc. A typical example are the weird TTL inputs having internal pull-up resistors.

That is why, in these cases, they connect a "pull-down" resistor… but this is not the best solution.

"3-pole (SPDT) switch"

All these problems can be perfectly solved if the digital output acts as a 3-pole switch that switches the output between Vcc and ground.

Transistors are 2-pole switches. Unfortunately, there are no electronic devices with such a 3-terminal output. There are only devices (transistors) whose outputs (collector-emitter, drain-source) act as the humble 2-pole switch. What do we do then?

Composed 3-pole switch. Like in electrical circuits, we can assemble a 3-pole switch by two 2-pole switches with a common pole… and switch them in the opposite direction (never both "on").

CMOS output stage presented as an SPDT switch. So, in the CMOS configuration, a 3-pole composed transistor switch is assembled by two separate transistors acting as 2-pole switches.

"Potentiometer"

The problem of the SPDT configuration. The 3-pole switch would be a tempting explanation but it has one major drawback - it is not possible to implement :-) The problem is at the time of switching when both unwanted situations are possible - both switches are "on" (short connection) or "off" (undefined output voltage) at the same time.

Potentiometer instead SPDT. That is why, the better explanation of the CMOS output stage is to think of it as a potentiometer where the input voltage "moves" the wiper from the ground to the Vcc rail.

Transistors are 2-terminal variable "resistors". But there are no semiconductor devices acting as 3-terminal potentiometers. There are only devices (transistors) whose outputs (collector-emitter, drain-source) act as the humble 2-terminal variable "resistors" (rheostats). What do we do then?

Composed potentiometer. Like above, we can assemble an "electronic potentiometer" by two "electronic rheostats" with a common point… and control them in the opposite direction. But, in contrast to the "SPDT configuration", here we make it so that they overlap at the time of transition. The two transistors will be "semi on"; so the power supply will be not shorted and the output voltage will not be undefined.

CMOS output stage presented as a "composed potentiometer". So, in the CMOS configuration, a 3-terminal "composed potentiometer" is assembled by two separate transistors acting as 2-terminal "variable resistors".

Answer 3

For now I'm interested in learning why the very simple NOT gate (inverter) is designed with 2 CMOSFETs. Just conceptually, not the math of it (if that's possible). Why not just one PMOSFET (P-type MOSFET)?

As hacktastical pointed out in his answer, it's entirely possible to build an inverter using only a single MOSFET (either N or P type).

He also pointed out one reason CMOS is preferred: power consumption.

But power consumption isn't (by any means) the only reason to prefer CMOS. Another reason relates to integrated circuit fabrication.

If you're accustomed to thinking in terms of discrete devices, resistors are cheap and simple, and transistors are complex and expensive (or at least, not nearly as cheap).

In an integrated circuit, however, quite the opposite is true. Transistors are small and simple, and resistors are a giant pain. To create a resistor, you generally use doped polycrystalline silicon. This has a number of problems though. First of all, even slight changes in doping level can change the value of your resistor quite a bit. Second, the resistance often has a pretty high thermal coefficient--to the point that even as you (try to) pass a pulse through it, the current warms it enough to change the resistance significantly, so it turns your square wave into something closer to a sawtooth wave. Finally, they tend to take up quite a lot of space--this is especially true if you need different resistances. To avoid have a lot of different doping levels, you usually end up settling on one doping level, then using physical geometry to give a higher resistance, which frequently leads to a fairly long, serpentine trace to get the right resistance.

So, in an IC, a resistor is actually much more expensive a transistor. In fact, a single resistor may easily be more expensive than an entire CMOS inverter.

Another point to consider is simply speed. This does relate to power consumption, to some degree. For the moment, let's consider an NMOS inverter with its input low so the output will be high. In this case, the transistor is not conducting, so let's just leave it out of the circuit. What we have left looks like this:

^{simulate this circuit – Schematic created using CircuitLab}

The capacitor represents the capacitance of the circuit this is driving. But, this should look pretty familiar--it's a basic RC low-pass filter. The speed at which we can charge that capacitor is controlled by the value of the resistor--the larger the resistor, the longer it takes to charge.

This is where power consumption comes into play: to reduce the rise time, we need a smaller resistor. But a smaller resistor also means that when the input to the FET goes high so the output is low, the FET has to conduct more current through to ground.

Thus, we fairly quickly reach a point where a faster circuit consumes a lot more power--and we need to use bigger transistors to handle the amount of current that's flowing when the transistor is conducting. And that means our circuit isn't just more power hungry, but it also consumes more chip area (and remember, due to the resistor, it's already big), so a given amount of logic becomes substantially more expensive.

You can also get a bit of a problem with symmetry. That is, when the transistor conducts, its resistance is quite low, so it charges/discharges the circuit its driving at one speed. If the resistor you use has a higher value than that, you'll get a situation where you have a significantly longer rise time than fall time (or vice versa, depending on whether you use PMOS or NMOS).

You still run into a tiny bit of this problem with CMOS--NMOS transistors are generally a little "better" than PMOS, so you get a tiny bit of asymmetry, which can be a problem at really high speed--but it's still a lot closer to symmetric than almost any practical resistor/transistor combination.

Summary

Resistors are simple as discrete components, but on an IC, they're a massive pain. With single ended circuits, power consumption is not only higher, but generally has a pretty serious speed trade-off as well, and if you pursue speed, you can end up drawing enough current that you need bigger transistors that significantly reduce circuit density, increasing costs.