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I have created a SPI controller in Verilog and I want to support all 4 SPI modes (clock phase and polarity options). It's easy enough to do this by changing the always block to be posedge or negedge and by inverting the SLCK signal.

I know that I can use 'ifdef to create a conditional compilation, but I'm not sure how to use a parameter to do this. It is important to use a parameter because I want to package the IP using Vivado, which only detects parameters as options, not 'define statements. I'm not sure if this is possible but if it is, then it saves a lot of time (adding one IP to block design and changing its parameters instead of creating a file, copying over source code, and then changing definitions manually).

Essentially what I want to do is something like this (I know this won't work):

parameter phase = 0;

if (phase == 0)
    always @(posedge clk)
else
    always @(negedge clk)
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1 Answer 1

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There is no need to do this. You can use the parameter to invert the clock. Since it is phase is not a changeable signal, it does not introduce any skew.

parameter phase = 0;

wire pclk = clk ^ phase;

always @(posedge pclk)
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  • \$\begingroup\$ are there any downsides to this approach? for example, does it add timing delay or maybe use more logic blocks? \$\endgroup\$
    – OM222O
    May 9, 2022 at 2:08
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    \$\begingroup\$ I have used many synthesis tools, but not Vivado. Any good synthesis tool optimizes parameters out of the hardware as part of constant propagation or constant folding similar to what a software compilers do. See en.wikipedia.org/wiki/Constant_folding \$\endgroup\$
    – dave_59
    May 9, 2022 at 3:06

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