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I want to build a low-noise and low-frequency preamplifier with the first-stage opamp of type LT1028 offering an input-referred voltage noise density of about \$2~\mathrm{nV}/\sqrt{\mathrm{Hz}}\$ at \$1~\mathrm{Hz}\$. Together with further stages (not shown here), an overall gain of \$80~\mathrm{dB}\$ will be implemented later. Therefore, a high pass filter is needed where the lower cutoff frequency should be \$<1~\mathrm{Hz}\$ (higher cutoff frequency not relevant here).

As shown in the following LTspice simulation, a capacitor with a value of \$10~\mathrm{uF}\$ would be basically sufficient together with a \$1~\mathrm{M\Omega}\$ resistor: enter image description here

However, due to the current noise at the non-inverting input of the opamp of about \$40~\mathrm{pA}/\sqrt{\mathrm{Hz}}\$ at \$1~\mathrm{Hz}\$ an additional voltage noise at the opamp's input of approximately

\$\frac{1}{2 \pi \cdot 1~\mathrm{Hz} \cdot 10~\mathrm{uF}} \cdot 40~\mathrm{pA}/\sqrt{\mathrm{Hz}} = 637~\mathrm{nV}/\sqrt{\mathrm{Hz}}\$

occurs: enter image description here

So far, my only idea to overcome this high noise is to heavily increase the capacitance to \$10~\mathrm{mF}\$, leading to the desired overall input-referred voltage noise density slightly above \$2~\mathrm{nV}/\sqrt{\mathrm{Hz}}\$ at \$1~\mathrm{Hz}\$: enter image description here

In principle, I could utilize several non-polar electrolytic capacitors in parallel, like e.g. this one: https://eu.mouser.com/ProductDetail/United-Chemi-Con/BSME250ELL222MMP1S?qs=N30EEhHmMqFPj%252BbaPkR%252BMw%3D%3D

This feels wrong, though, because you would normally use temperature-stable ceramic or film capacitors for such purposes. However, this is not possible here due to the high capacitance.

Could you still use bipolar electrolytic capacitors in this case or what would you do differently?

Also, I wonder how such high-pass input stages are implemented in commercial measurement devices, such as the SR785 from Stanford Research Systems.

Edit: Summary of specifications:

  • Amplifier with a total gain of \$80~\mathrm{dB}\$ (here we only consider the first stage with a gain of e.g. \$20~\mathrm{dB}\$)
  • Lower cutoff frequency: \$<1~\mathrm{Hz}\$
  • Upper cutoff frequency: \$>100~\mathrm{kHz}\$
  • Input-referred voltage noise density for \$f \ge 1~\mathrm{Hz}\$ and \$f \le 100~\mathrm{kHz}\$: < \$5~\mathrm{nV}/\sqrt{\mathrm{Hz}}\$
  • Source impedance: \$\le 50~\Omega\$
  • Maximum DC level at amplifier input: \$12~\mathrm{V}\$ -> DC block in front of first amplifier stage required
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  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. \$\endgroup\$
    – Voltage Spike
    May 11 at 3:13

2 Answers 2

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Adding the specifications cleared things up greatly.

You have parameters that are at odds with each other which is expected. I ran a few different runs using the .step statement with different input capacitors while holding the high-pass filter (HPF) corner frequency at approximately 1 Hz to see if there is an optimal capacitance for the HPF.

  • Capacitance around 100uF ends up being very noisy due to the noise current.
  • Capacitance above 2000uF ends up becoming noisier since resistor for your RC HPF becomes very small and forms a voltage divider with the 50 ohm source resistance which reduces the gain (why it gets noisier).
  • Somewhere around 1000uF seems to have good noise response without loosing too much gain. You might want to play around with this to see if you can do better.
  • When raising the capacitance to 10mF (10000uF), the gain goes higher than expected. I'm not sure why that's happening.

enter image description here

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Always start with overall expectations or Design Specs, then break it down into blocks for all interfaces.

I see no reason why the 1st stage is not DC coupled and lower impedance than 1M such as 10k to 47k using a differential amplifier config. This is preferably done with precision matched R ratios pairs for good CMRR, albeit expensive resistor arrays. You do have to worry about CM noise too and spec what your PSU CM noise levels are.

Then AC blocking is easily done in the cascaded stages with smaller caps and bigger R values where SNR exceeds your TBD specs.

Superbeta BJT's were known to have lower noise due the gold content like the 2N5088, and low noise JFET front ends are also common. You have plenty of options after you define all your design specs.

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  • \$\begingroup\$ As I explained above: A DC block after the first amplifier stage is not possible in my case, because I want to detect very small AC signals in the nanovolt regime (using cross-correlation) with a high DC level at the same time. Therefore the DC filter must be implemented directly at the input of the circuit. \$\endgroup\$
    – Charly
    May 10 at 19:49
  • \$\begingroup\$ ok TY but your specs are not clearly listed in the question. such as source DC, AC, BW and Z(f) and SNR of source. \$\endgroup\$ May 10 at 19:54
  • \$\begingroup\$ I added a summarizing list of the specifications. \$\endgroup\$
    – Charly
    May 10 at 19:57
  • \$\begingroup\$ Do you plan on using Cryofree dilution refrigerator for the resistors? zhinst.com/sites/default/files/… \$\endgroup\$ May 10 at 20:12
  • \$\begingroup\$ I am not familiar with the term "cryofree dilution refrigerator" or I do not know exactly what is meant by it (I am not a native English speaker). But the content of the ZI pdf, at first glance, seems to be exactly like what I plan to do and which is explained very good here: arxiv.org/pdf/1003.0113.pdf. \$\endgroup\$
    – Charly
    May 10 at 20:20

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