If you have length matching on the inner layer of 4 layer board: Do you need any minimum or maximum distance to the adjacent layers above and below? Are there any rules of thumb?

Also is there any minimum or maximum distance to any polygon on the same layer as the length matching/differential pairs? Any rules of thumb?

P.S. added imageexample

  • \$\begingroup\$ Normally, on a 4 layer board, the inner layers are just power and ground planes. The routing takes place on the outer (top and bottom) layers. \$\endgroup\$
    – Aaron
    May 11, 2022 at 21:58
  • \$\begingroup\$ Maybe post a screen shot of what you are talking about? \$\endgroup\$
    – Aaron
    May 11, 2022 at 21:58
  • \$\begingroup\$ @Aaron I don't think this is a blanket rule. I have seen a lot of cost-optimized 4-layer boards with ground poured on the outer layers and signals and power on the inner layers. Obviously care needs to be taken to not route under the components but this often provides tighter coupling to the reference planes. \$\endgroup\$ May 11, 2022 at 22:00
  • \$\begingroup\$ @mooshoomatt, Agreed, thus why is said, "Normally". It's the designers copper, they can do whatever they want with it. \$\endgroup\$
    – Aaron
    May 12, 2022 at 3:00

1 Answer 1


What is your stackup? Where are you routing power and ground? What kind of interfaces are you routing? How fast? These are just some of the questions that would better inform answers to your questions.

Question #1: How to determine the required spacing between length-matched signals or differential pairs and the adjacent layers?

If you are length matching that implies that the interface is probably fast enough to require controlled impedance. So, the trace width and distance to adjacent reference plane is determined by the desired trace impedance. Trace Impedance Calculator

Also take not of how close your signal layers are to other signal layers. Ideally for a 4-layer stackup, you want your signals close to your reference layers and far away from any other signal layers.

Question #2: How to determine the required spacing between length-matched signals or differential pairs and polygons/copper on the same layer

This one is more of a manufacturing constraint. Your PCB manufacturer will tell you what the track-to-polygon clearance is for their fabrication process. As for signal-to-signal clearance, the PCB manufacturer will give you a number here as well. However, placing tracks as close together as possible may contribute to crosstalk issues which is why it is better to keep tracks away from eachother wherever possible.

  • \$\begingroup\$ Thank you. added image now. for question 2: see image. Is there no rule except for the fabrication process? My line of thought is that if one of the differential pairs is close to a polygon on the same layer. Then would not that pair have a diffrent impedance than the other differential pair because it is closer to GND in the polygon? So should there not be a rule to make sure that that the impedance is "off" for the signal lines? Is it a good idea to use polygon cutout to make sure only above and below planes are affecting the impeanse of the lines? \$\endgroup\$
    – exzb
    May 11, 2022 at 22:28
  • \$\begingroup\$ @exzb The ground pour copper inside the same plane (layer) as your signal does not have nearly as much of an effect on the impedance as does the adjacent layers. There is a reason that your CAD software does not take other geometry on the same layer into account. I doubt you need to add additional cutouts to maintain accurate impedance. As for a rule of thumb, if you really want one. I've heard many people say that the clearance should be 3 x trace width for sensitive signals and 5 x trace width for differential pairs. I hope that helps. \$\endgroup\$ May 11, 2022 at 23:50

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