How does current travel in multiple vias from one layer to other?

For example, we connect four vias, each of which has a limit of 1.3A each from power plane to sink device. If the sink draws 4A of current, will it be separated between these four vias like 1A each or will the first via which receives the current from source be more than other vias? Will the first via fail?

  • 2
    \$\begingroup\$ Depends. Are you talking steady state 4amps, or is there any switching? If so, the answer will be frequency dependant. If is steady state, it'll be path of least resistance, if all four vias are identical, and the route for each is the same, then they'll share it equally, otherwise it's a parallel resistance calculation. \$\endgroup\$
    – Puffafish
    Commented May 12, 2022 at 8:05
  • \$\begingroup\$ You may use special vias with a larger drill diameter only for this purpose, their current limit should be higher. \$\endgroup\$
    – Uwe
    Commented May 12, 2022 at 9:42
  • 2
    \$\begingroup\$ There have been several discussions recently about using multiple wires or pins in a connector to share current. Using multiple vias to carry current is just a variation on that. You might want to search for those tags. \$\endgroup\$
    – SteveSh
    Commented May 12, 2022 at 12:46

6 Answers 6


It can be a concern in some cases. It's sometimes worth breaking out components to see. That is, replace each PCB trace and via with its equivalent resistance (or impedance if you're dealing with AC) and simulate. Here's an example:

Imagine you have a 5 inch run that needs to go from the top to the bottom of the board, and you put 4 vias at the 1/2/3/4 inch marks.

4 amps over 1 oz/square foot PCB, 100 mil traces, 5 inches long. Using the default via settings from here for estimated via resistance. One inch of trace here has a little under 5mOhm of resistance. And the vias about 0.75mOhm of resistance.


simulate this circuit – Schematic created using CircuitLab

When you work out the currents through the vias, something funny happens. The first and last vias are taking 1.87 A each, and the two middle vias are only taking 130mA each. (I have the currents set up in the simulation. Run->DC Analysis. I don't know how to show them directly in the answer.)

This is mainly because the vias don't actually have that much resistance overall. It's much higher per unit length, but vias aren't that long. So if you squint a little bit you have two parallel resistors shorted together every so often - and of course you don't have much current flow between the two except at the start and end.

You want the vias close together if possible, or star-connected. Normally this makes no difference. Every once in a while, it does.

(As an aside, trace widths / lengths / etc here are completely made up. Please don't blithely use these numbers.)

  • 1
    \$\begingroup\$ Of course for 'full' marks you want to do a full FEA of the board, but this is a decent approximation in some circumstances. \$\endgroup\$
    – TLW
    Commented May 12, 2022 at 23:46
  • 1
    \$\begingroup\$ Consider also that copper has a positive resistance thermal coefficient, 0.00393/C to be precise, that provides some negative feedback, which can help balance out the currents if the top copper has a low enough resistance \$\endgroup\$
    – diegogmx
    Commented May 17, 2022 at 18:15
  • \$\begingroup\$ @diegogmx - interestingly, that doesn't actually help (much) in this case. Even if you double the resistance of the first and last vias (to 1.5mOhm) you still get 1.755/0.245/0.245/1.755 A through the vias. And because R14/R15/R16 and R17/R18/R19 are carrying nearly the same amount of current (as a consequence of the middle vias carrying little current) they 'should' end up at approximately the same temperature. \$\endgroup\$
    – TLW
    Commented May 17, 2022 at 23:20
  • \$\begingroup\$ "if the top copper has a low enough resistance" is another way of saying "if the vias are spaced close together". \$\endgroup\$
    – TLW
    Commented May 17, 2022 at 23:21
  • Current splits into all available paths but tends to split more in the lower impedance paths => the current in a given path depends on its impedance and on the impedance of the other available paths (see "current divider").

  • The impedance of a path depends on many factors:

    1. The resistance of the tracks (proportional to length/( width X copper thickness)) and of the vias (proportional to depth/(hole diameter X plating thickness)). Copper pours/planes can be considered a bunch of different available paths around holes.
    2. Temperature: the resistivity of copper increases with temperature, so if there are temperature gradients on your board, the current distribution will change.
    3. (For AC currents): the inductive part of the impedance depends on the geometry of the tracks and vias (thin long traces are more inductive) and the loop area of the return path: if the "back" current cannot go directly beneath the "there" path because it is forced in a track or around holes in a plane, the inductance will increase.
    4. (For AC currents): the capacitive part of the impedance depends on the geometry and layout of the stackup and of the tracks/vias: the closer the path is from the GND plane or other planes and signals, and the bigger the areas that are close, the higher the capacitance.
    5. Obviously if different paths go through different components, the impedances of these components count.
    6. ...

The water analogy doesn't always apply, but it may help you here: if you have several pipes of different diameters coming out of a single pipe, the flow of water will split in a proportional way more in the larger pipes but will not leave any pipe empty. enter image description here

Note: as you can infer from this, there is no real 'current limit' to tracks and vias - only limits we set to ourselves to only allow the tracks considered to reach a certain rise in temperature in a simplified, isolated, case. In your example, if for the reasons mentioned above one of your vias and the path to it have less resistance than the others, it will conduct more amps thank the others - but it will heat up more, so this difference in currents will decrease until steady state is reached.


There's a video by Robert Ferenec that explains this in simulation, you can start at 38:24 to see current flow in multiple vias, depending on their placement. https://www.youtube.com/watch?v=56FvQX63Ea0

Basically, it depends what is the path of least resistance (DC only)


We train Ohm's Law and resistance so hard that we forget about the inverse of it: Conductance.

Conductance uses the unit siemens and it is the 1/ohms. So a 10 ohm resistor has 0.1 siemens of conductance,

With parallel paths, current flows in proportion to their conductance.

So if you have 3 paths of 10 siemens, 20 siemens and 40 siemens, and 7 amps flowing, the current of each path will be 1 amp, 2 amps and 4 amps respectively.

That's easy.

You already do all this math regularly. You just perceive them as parallel paths of 100 milliohm, 50 milliohm and 25 milliohm respectively... and it's really hard mentally to see the answer from that perspective.

So if you have specimen boards to spare, you can wreck three of the via's on each board and determine the impedance of the via under test, flip it to conductance, and there you go.

And a little bit of overdesign never hurt.


each of which has a limit of 1.3A each from power plane to sink device.

Conductors don't have a 'limit' as such. As the current flows, they will get hot. They will also lose heat to the ambient. Their temperature affects them and their substrate. The 1.3 A is a rating, which is calculated under certain assumptions, to cause no damage.

The vias will share current to the extent that the tracks top and bottom equalise the voltage to their ends, and that the resistance of the vias matches. If the vias are closely spaced, they will likely share reasonably well. If they are spaced out in a line, and the connections are to one end and the other end of the line, then they will also share well. If there's a long line fed from one end, they won't share well.

current in ----------------------------------
               |       |           |       |
current out----------------------------------

current in ----------------------------------  
               |       |           |       |  
           ---------------------------------- current out  

reasonable for the vias, but why are the tracks so long?
current in ----------------------------------
current out---------------------------------- 

This is for DC and low frequency, and resistive considerations. Similar high frequency and impedance considerations exist.

As vias are fairly cheap, you could always add a few more if you are concerned that some may not 'pull their weight'.

  • \$\begingroup\$ Your first 'good' case (spaced out vias with current in on one end and current out on the other) is actually bad. See my answer for an example. The first and last vias will take most of the load, assuming the via resistance is less than the resistance of a trace segment. \$\endgroup\$
    – TLW
    Commented May 12, 2022 at 23:45
  • \$\begingroup\$ "Conductors don't have a 'limit' as such." That's not completely correct. Even if you somehow manage to keep the trace or wire cool you will eventually encounter a limit due to electromigration. However, that limit is so high for normal traces you're unlikely to hit it outside of ICs. \$\endgroup\$
    – BrtH
    Commented May 14, 2022 at 12:46

At low frequencies and at DC the current will follow the path of least resistance, and at high frequencies the path of least inductance. In either case, it is necessary to take into account the geometry of the copper connecting the vias to one another. Whether they are traces or planes, their respective resistance and inductance will affect the distribution of the current to the vias.


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