I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating 25MHz clock frequency. But now I want to go up and generate a VGA 800x600 signal and for this is necesary to have a 40MHz clock. I'm using Quartus Lite 20.1 and I dont know how to achieve this step. I'm newbie with FPGA and Quartus software. Thank you.

  • \$\begingroup\$ 0 I don't know enough of the details to write a good answer, but I can suggest a direction for you to research. I see that the FPGA you are using has 2 PLLs. Using a PLL could be a good way to generate a 40 MHz clock output based on a 50 MHz clock input. \$\endgroup\$
    – B Pete
    Commented May 13, 2022 at 1:08
  • \$\begingroup\$ You'd typically use a PLL to do this. The EP4Cx6E22 device has 2 multipurpose PLLs which would be suited. You'll also need to ensure that you watch the 'LOCK' bit (essentially a PLL valid/ready bit) to know that the desired frequency arrangement is met. \$\endgroup\$
    – M1GEO
    Commented May 13, 2022 at 1:28
  • \$\begingroup\$ Thank you very much. I understand what you suggest, But I dont know how to doit in Quartus :( \$\endgroup\$ Commented May 13, 2022 at 3:18

1 Answer 1


Use a PLL. Divide your 50 MHz by 5 to get 10 MHz. Then configure the feedback divider in the PLL to divide by 4, and you'll get 40 MHz.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.