I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating 25MHz clock frequency. But now I want to go up and generate a VGA 800x600 signal and for this is necesary to have a 40MHz clock. I'm using Quartus Lite 20.1 and I dont know how to achieve this step. I'm newbie with FPGA and Quartus software. Thank you.