I wanted to make a device that has a USB A and a USB C connector on apposing sides of the PCB, similar to the attached image. These USB connectors would be connected to the same USB port, the MCU I am using has only one USB port. The connection type would be USB 1.1 full speed. One of the connections can be made under the critical length, the other one I would have to run matched impedance controlled traces to. I am just wondering if I have to worry about the traces for the connection that is not being used, acting as a capacitor or inductor. Is there anything else I have to worry about?
USB Full Speed is simply symmetrical* 12MHz LVCMOS logic levels. It's very far from a signal quality concern; fast enough to need proper cables, low enough voltage to need shielding, but at the PCB level, trace width, and length (up to a generous limit) are largely irrelevant.
*Except when they're not; the start and stop symbols are asymmetrical (both lines moving in the same direction, not complementary). Which is another reason why USB is difficult to filter noise off of, and why contiguous shields are mandatory.
You will have no problems, with a board sized as pictured.
However, if you're expecting performance up at High Speed, these concerns are more justified. Still not a problem on a board that size, I think (the stub length of either connector will be, what, a cm or two, at most?). Super Speed will probably not work with such stubs. (But, since SS isn't supported by USB-A, it would be quite strange to route those pairs to a connector that doesn't even have pins for them. :) )
The deciding factor is if a stub length or mismatch length is a substantial fraction of a bit-time: for High Speed, this is in the low ~cm. Trace mismatch isn't extreme in most situations: the usual worst case is thin traces on a thick substrate (i.e. 2-layer board): the differential impedance is in the 150-200 ohm range, when 90 or so is required; so, it's only a 2:1 mismatch, not at all extreme. Mismatch becomes proportionally more significant when it's worse -- but it's hard to even conceive of a situation with, like, 600 ohm twin lead, on a PCB with ground plane (good luck with that?!), and even then that's a ~5x mismatch so only 5x more sensitive, or a problem for "low ~cm" / 5 -- say, >3mm worth.
In general, when mismatch is some factor, the critical length is shorter by the same factor; for example, we can apply this to the layout of switching converters, where the impedance might be a mere 5 ohms ballpark (say for a 5V 1A converter). Relative to say ~100 ohm traces, that's a mismatch of 20x. If the converter's maximum harmonic frequency is ~200MHz (typical for modern switching regulators), the critical length is a wavelength of ~4GHz. So, a cm or so -- hence why we minimize layout area of these circuits. The same logic applies to most digital communications, and so we minimize the layout area for them as well, with the scale factor (for what counts as "minimized") given thusly.