# I don't understand JFET/this diagram Associate CET study guide

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I need help understanding JFET amplifier circuit I have a lot of questions that maybe basic questions I'm sorry.

This is a N-channel Jfet so it has negative voltage but what does that even mean “negative voltage ” (image 2 [Image2]and image 3 [Image3])

Image 2 what is amplification factor is it the max it can amplify or is it amplifying that amount in this example. Also what is I,d constant in the mu equation or maybe why is I,d constant?

What is dynamic drain resistance and why is V,gs constant?

I don't know what the first paragraph Image2 is saying “bias” I know a bias can be forward or reverse is that what the diagram show (image 1) what is the last sentence explaining “short,,; I,d is maximum”?

How did they chose their numbers in paragraph 2 and “establish a V,gs to swing +1v -1v ”what is this and why

Paragraph 3 they chose -2v for V,gs why. If it because of the graph I don't know how to interpret it

RL on the diagram (image 1) is 13.3k they explain why in paragraph 3 but why is the resistor source related to the drain idk could be a dumb question Image1

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• The gate draws almost no current so Vg=0 but Id raises source voltage across Rs thus Vgs is negative. If Vgs=0, Id=Idss May 14 at 4:09