I'm writing a FIR filter in Verilog, but the circuit does not synthesize. I've tried many different things, but ultimately it doesn't seem to want to synthesize the sum of an array.

I have tried splitting up the sum into 8 or 16 or 32 different sums; then summing those.

As soon as I try to use the resulting sum to drive another register, it starts having trouble synthesizing.

Initially I tried doing the summation and FIR multiplication at one time:

sum = 0;
for (ii=0; ii<2048; ii=ii+1) begin
    sum = sum + taps[ii]*signalHist[ii];

This didn't work(synthesis never completed). So I tried splitting the multiplication into one loop and triggering the sum on the next clock cycle. Still no good.

Then I tried manually splitting the sum into many different sums (eg. 16 or 32) - then summing those 32 sums on the next clock cycle. This seems to synthesize as long as I didn't use the result to drive anything else in my design, but as soon as I try to use that final sum to drive another register I get synthetization problems (Quartus spins forever).

for (ii=0; ii<2048; ii=ii+1) begin
    product[ii] <= taps[ii]*signalHist[ii];
productTrig <= ~productTrig; //triggers sum on next clock cycle

The first part of the sum was as follows, summing 64 points at a time below (I tried 128, 256, etc):

sumOfItAll[0] = 0;
sumOfItAll[1] = 0;
SumOfItAll[31] = 0;
for (ii=0; ii<64; ii=ii+1) begin //4096 or 256 loops
    sumOfItAll[0] = sumOfItAll[0] + product[ii];
    sumOfItAll[1] = sumOfItAll[1] + product[ii+1*64];
    sumOfItAll[31] = sumOfItAll[31] + product[ii+31*64];
sumOfItAllTrig = ~sumOfItAllTrig;// triggers the second sum of these 

And the second part of the sum, triggered on the next clock cycle:

sum = 0;
for (ii=0; ii<32; ii=ii+1) begin
    sum = sum + sumOfItAll[ii];
doneReading = ~doneReading; //triggers the sum to be output to DAC register

All this splitting the summation up manually; and it seems to have the same synthesis issues - Quartus just spins forever.

If I don't use that resulting sumOfItAll[ii] (or only use sumOfItAll[0], for example) it synthesizes just fine. But that, of course, is not what I am trying to do.

Is there something fundamentally wrong with my HDL, or what I'm trying to do with Verilog? Is there any way I can get these 2048-point (or more) sums to synthesize?

Is there a way I can get Quartus to do this by letting it use more clock cycles?

  • 1
    \$\begingroup\$ Before you try to synthesize, you need to make sure it simulates the way you expect it to. \$\endgroup\$
    – toolic
    May 14 at 21:03

1 Answer 1


I agree with the comment from a user. You should simulate your design in a Testbench before going to synthesis.

My feeling: Your filter is 2048 taps right? This is very large and don't expect the tool to be able to meet timing for whatever frequency in a single clock. You have to pipeline it in several clocks.

I recommend to use the Xilinx FIR compiler IP. It is configurable and will do the optimization stuff for you. It can be enough for your need.

If you really want to code it, try to make an adder tree.

Note that it is important that the multiplication operands bit length match with FPGA DSP cells size.

  • \$\begingroup\$ Thanks. Im using Altera/Intel, will the Xilinx tool still work? The code does simulate correctly. I have splitting up the addition into multiple clock cycles, but I suspect Im somehow not telling the compiler that the steps will be sequential, and its trying to build the circuit assuming they may happen simultaneously. Ill read more into pipelining and try to figure out what Im doign wrong. Also, Im using all integer (signed int[]) math; so not using DSP cells. I had hoped that this would simplify things. \$\endgroup\$ May 16 at 15:51
  • \$\begingroup\$ If you go for an IP core, it will be only compatible with the vendor one yes. If hand coded, maybe try to look for systolic fir architecture \$\endgroup\$
    – gotchi85
    May 16 at 18:30
  • \$\begingroup\$ Better use signed or unsigned signals in bits than integers \$\endgroup\$
    – gotchi85
    May 16 at 18:32

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