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I was doing some experiments using the following IGBT:


I used it to drive a load of ~4.7ish Ohm and ~140ish µH from a capacitor bank of 2350µF. Each experiment consisted of charging the capacitor bank to a certain voltage and then applying a single pulse of varying length to the gate driver (MCP1407, for schematic I replaced it by the next best thing I could find in the components list), Datasheet:


For maximal switching speed, I did not use a gate resistor, but used a 15.3V Zener soldered directly on the leads to protect the gate from eventual spikes. The inductive load had a diode across (near IGBT) to limit voltage after shut-off. The gate driver was powered by a 12V lead acid battery. I omitted decoupling caps from the schematic (1µF for the gate driver and 11.2nF parallel to the capacitor bank)

As I was increasing the voltage and pulse duration, the IGBT decided to suddenly identify as a 0 Ohm resistor (<3mOhm). All other components survived (except the flimsy wire to the load, which melted in one spot (deliberately chosen weak point)). The gate is now a 16 Ohm resistor.

I gathered the following data on the experiments:

last experiment before the boom: capacitor bank charged to 450V, a pulse of 500µs (or 5xxµs?, I'm not 100% sure the last 2 digits were 0, unfortunately that was the one number I forgot to write down and only re-added it afterwards from memory). The pulse discharged the capacitors to 432V, dumping ~19J at ~84.6A average current (assuming 500µs and capacitor ratings are accurate).

The next experiment of 720µs pulse duration @450V resulted in a boom. Interestingly, the IGBT has no visible damage and magic smoke only escaped from the wire. Afterwards, the capacitor bank had ~120V remaining.

Now the question: what happened? What did I do wrong? I thought the datasheet said 160A is fine, or is that the wrong value to look at? However, SSOA also states 480V 100A. Do the other conditions to that value matter/in which direction is a deviation from them safe? Or was the pulse duration of 720µs too long? How would I go about calculating the max duration from the thermal response data in the datasheet? Or is there such a thing as switching it too fast? Or were 12.5V for the gate driver too low? The data from 500µs does not show a dramatic voltage drop on the IGBT, at least not by my calculation: At an average 441V(-4V IGBT drop), expected would be 93A for a 4.7 Ohm resistor or 87.2A with the measured total resistance of wires, contacts and load (5.01 Ohm). Now add ~29µs inductive current ramp-up and a bit of cap ESR and the numbers match.

As I would not like to burn through more IGBTs finding out, I would like to know what I did wrong/what I can do so it does not happen again. Unfortunately, I don't have a DSO that could capture these events.

  • \$\begingroup\$ Where are your design specs? and limits to failure? and where is your power supply and specs? \$\endgroup\$ May 16, 2022 at 18:29
  • \$\begingroup\$ Which ESD precautions did you not follow? Why did you think direct gate drive was valid considering Ciss? \$\endgroup\$ May 16, 2022 at 19:29

1 Answer 1


SRF (LC) ~ 250 Hz
Zo (LC) ~ 250 mohms
R=4.7 , Qs= 0.25/4.7 over-damped

Rce (@ Tc=25 'C) = 2.6 V/100 A = 26 mohms + Vt=1.4 V (nominal from spec. Figure 4)
Rce (@ Tc=150'C) = 3.8 V/80 A = 48 mohms + Vt =1.0 V

Imax < 450 V / 4.7 ohms= 96 Amps approx. 96 A * 26 mohms = 2.5 V thus Imax is reduced slightly.

Max Power
SSOA 100A limit (repetitive)

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10 ohm Gate resistor and 15V pulse will improve margins.


SOA margin was minimal and compromised by 0 Ohm Rg.


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  • \$\begingroup\$ So adding a gate resistor also helps? By what mechanism? I thought faster is better as there is less time where the IGBT has both high voltage and high current across it? Sorry, I'm still learning. \$\endgroup\$
    – HL65536
    May 17, 2022 at 6:07
  • \$\begingroup\$ there is also a large gate Q which also has a series R and thus V^2/R=P in added gate power. So the optimal is where resistances are about matched when driving near limits. If not given, always use what they recommend in test results. If you derate SOA significantly and have 0R with ESL and Ciss, beware of Q and SRF as it may ring. Thus overdamping degrades Pd on output but matched resistance reduces ringing from gate Vgs control. Lower the series R , higher the Q, which cannot be shown in my Simulator unless you add the 0.8 nH/mm and Ciss and Rg etc \$\endgroup\$ May 17, 2022 at 13:29

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