Voltage controlled 555 bistable operation

Question

[Updated with working schematic!!!]

I have a circuit which I tried to adapt from the 555 bistable configuration to have the 555 states controlled by input A and B; B always goes high before A.

I am trying to have the reset pin set high when B goes HIGH (1.5V) and since A would start HIGH, I expect that the output is HIGH.

When A finally goes HIGH (B will still be HIGH) the trigger pin voltage becomes 2V which is above 1/3Vcc, I expect the output to go LOW since the trigger pin has been pulled HIGHer than 1/3Vcc.

I tried the circuit below and an LED hooked to the output stays on through out, it doesn't change even if I try to pull the trigger pin to a significantly high voltage.

The overall truth table I am trying to get out of the 555 is included below:

| A | B | Output|
| - | - | ----- |
| 0 | 0 |   0   |
| 0 | 1 |   1   |
| 1 | 0 |   0   |
| 1 | 1 |   0   |

Can someone please tell me what is wrong with this configuration and/or suggest a workaround using the 555?

Working schematic:

Hope it helps:) (sorry for the inconsistency in the circuits.)

Answer 1

To get the output to go low you need to take the reset pin high which removes the reset, then take the Trigger pin high (above Vcc/3) which removes the trigger signal, but the output will only then go low when you take the THR pin above (2/3)Vcc. This is the bistable operation.

The overiding signal is the RESET pin. The output will always be low when the RESET pin is low. If the RESET pin is held high then the output will always be high when the TRIGGER pin is below Vcc/3. But after the TRIGGER pin has been taken above Vcc/3, the output will remain high until THR is taken above (2/3)Vcc which will then force the output low.

If you tie the THR pin permanently to Vcc then, as long as RESET is held high, the output will be high when TRIGGER is below Vcc/3 and the output will be low when TRIGGER is above Vcc/3.

In short, tie THR to Vcc instead of GND.

Answer 2

Have a look at the lock diagram of the 555 from Wikipedia:

https://en.m.wikipedia.org/wiki/555_timer_IC

Pin 4 is a logic input to the SR flip flop, so you’re not getting the comparison action you’re hoping for. Only pins 2,5 and 6 can be used to compare analog voltages - I won’t detail the solution to your specific problem here because you’re doing good work trying to build this oscillator.

Also without a way to discharge the cap (customarily pin 7 is used for this feedback) your circuit will not oscillate, though I’m not sure this is the intent of the demo achematic you provided.

Answer 3

The 555 timer can be used as a stateless logic element, with the caveat that the threshold voltages of both inputs are different. This means reduced noise margins on input!

The necessary nugget of information comes from a footnote to Fig.8.2. Functional Block Diagram in the NE555 datasheet:

NE555's inputs are prioritized: RESET has priority over TRIGGER, and TRIGGER has priority over THRESHOLD.

Thus, the truth table looks as follows:

RST|TRG|THR|OUT
---|---|---|---
 0 | x | x | 0
 1 | 0 | x | 1
 1 | 1 | 0 | NC
 1 | 1 | 1 | 0

Above, NC means "no change": the previously latched state is unchanged.

This is also shown in the datasheet, table 1:

To get rid of the latch behavior, THR has to be set high, eliminating one half of the truth table:

RST|TRG|THR|OUT
---|---|---|---
 0 | 0 | 1 | 0
 0 | 1 | 1 | 0
 1 | 0 | 1 | 1
 1 | 1 | 1 | 0

We get a circuit equivalent to AND with one inverted input:

^{simulate this circuit – Schematic created using CircuitLab}

We can also explore the other possible two-input combinations:

RST|TRG|THR|OUT RST|TRG|THR|OUT  RST|TRG|THR|OUT
---|---|---|--- ---|---|---|---  ---|---|---|---
 0 | 0 | 0 | 0   0 | 0 | x |0=R   0 | x | x | 0 
 0 | 1 | 0 | 0   1 | 0 | x |1=R  
 1 | 0 | 0 | 1   
 1 | 1 | 0 | NC  

The first table above, with THR=0, is not very useful, since we already have the same outputs when THR=1, except that the NC case would need to be handled. If NC were somehow forced to 0, we'd get the same table as with THR=1. If NC was forced 1, we'd get OUT=#RST - not a useful gate. The other two tables are not useful either: the 2nd one just passes RST to the output, and the third one has a constant output.

The other two potentially useful truth tables are:

   (NAND?)       
RST|TRG|THR|OUT   RST|TRG|THR|OUT
---|---|---|---   ---|---|---|---
 1 | 0 | 0 | 1     0 | 1 | 0 | 0
 1 | 0 | 1 | 1     0 | 1 | 1 | 0
 1 | 1 | 0 | NC    1 | 1 | 0 | NC
 1 | 1 | 1 | 0     1 | 1 | 1 | 0

In those tables, the NC cases would need to be "forced" to 1. The second table just becomes the one we got with THR=1, so it's not useful.

The first table could yield a NAND, if we could force the NC case to 1. That could be done using a diode and a resistor:

^{simulate this circuit}

We also get an output inhibit function without additional components, using the reset input:

^{simulate this circuit}

For reference, below is the internal schematic of the bipolar 555. The CMOS schematic is equivalent, so the function of all inputs is similar.

Could we use the control input? Tying it to either voltage rail is problematic, since the comparator output states will depend on the offset voltages of their input stages:

• when CONTROL is LOW,
  • a low TRIGGER and THRESHOLD is problematic;
• when CONTROL is HIGH,
  • a high TRIGGER or THRESHOLD is problematic.

So, one idea to exploit the CONTROL input would be to ensure that the voltage on it doesn't reach the rails.

This can be achieved by using a series resistor between a totem-pole output and the CONTROL input. We can then fix the TRIGGER level, at 2/3 VCC, and use the CONTROL input as-if it was an inverted TRIGGER input, thus obtaining an AND function:

^{simulate this circuit}