First of all, I've had no formal training as an electrical engineer, I've taught myself everything I know online, so this may be a stupid question. That said, I've designed an active PFC circuit using discrete components that appear to work in simulation when I pre-charge the capacitors with IC=200, because I don't have a model for the NTC.

This is the PFC circuit (Updated from the original post) PFC Circuit

These are the waveforms (Also updated) enter image description here

As you can see both the inductor and AC current waveforms do not look like they do in the application notes of a PFC IC. I can't seem to get them to look like they're supposed too without sacrificing the desired output voltage.

I want to build this thing for an full bridge converter that will be realized with a KA3525 using a gate drive transformer to switch the 4 MOSFETs.

From what I understand active PFC is not only to make the power companies happy (correct me if I'm wrong here), but it's also to have the correct amount of output power available to the DC-DC converter and to reduce the current stress on the DC-DC converter's MOSFETs.

I did try to use an LM339N to build the ramp generator in the oscillator section, but for some reason it was a complete fail (I don't know what it is, but I can never get those chips to work in reality).

Will this circuit (with line noise filtration and NTC in place of course) work in reality?

How can I fix the current envelope (is it necessary)?

  • 1
    \$\begingroup\$ Should I be controlling the duty cycle with the rectified AC wave form on a voltage divider or should I have a set duty cycle of 90% and let the overcurrent section handle that for me? \$\endgroup\$
    – user14828
    May 17 at 6:49
  • 1
    \$\begingroup\$ While I praise your ambition for learning and making things "with your own hand", is there any reason why you would not use a dedicated IC for this? At any rate, I would break the circuit into constituent sections and test them, separately. Then I'd try to couple two of them, again test, and so on. But the output voltage seems to grow fairly linearly, so you may want to test if the control loop works. You can shorten up the time spent simulating by adding ic=380 or similar to the output cap (BTW, one is enough, with the combined value). Also, C2 at the MOSFET seems questionable. \$\endgroup\$ May 17 at 7:01
  • \$\begingroup\$ @aconcernedcitizen I was going to mention why I'm not using a dedicated IC in the question among other things, but I didn't want to make it too long. Everything I see online is surface mount and are bound to a specific power output. Like I have FAN7554s which are really flyback controllers but it can be jimmy rigged into a PFC IC because it has a max duty cycle of 90%. The problem is that in the application note Rsense is .2 ohms (low power) and they don't provide a whole lot of data on how to use em. I don't have a whole lot of experience with ICs because I can't simulate most of them. \$\endgroup\$
    – user14828
    May 17 at 7:26
  • \$\begingroup\$ What I mean is that there are dedicated ICs that perform PFC, not some flyback coerced into cosplay. And you shouldn't care about the max duty cycle unless it's not enough/exceeds your specifications -- that's a matter of design. If your load's variations don't get there, no need to worry. In general, you can trust the datasheet test schematics to work. For more functionality, some adjustments may be needed, but as they are, they should work. But if you insist on using your design, then my comment above stays. \$\endgroup\$ May 17 at 7:45
  • \$\begingroup\$ @aconcernedcitizen or the simulation of ICs that I do have models of are prohibitively slow. For instance I'm actually using a FCH023N65S3, which I have the model for, but when I sim with it, it's like pulling teeth. I would never use the FET in the schematic, it's Rds is .9 ohms! Oh C2 was because I was experiencing some very low voltage high frequency oscillations at the gate and I forgot to delete it. The oscillations are in the low mV range, so they won't affect FET operation. I'm actually planning on building the control portion for a low voltage boost application first. \$\endgroup\$
    – user14828
    May 17 at 7:52

1 Answer 1


A person after my own heart!

Some tips:

  • You don't have to use full op-amp sections everywhere you need an amp/comparator. Example: the oscillator can be 3-4 transistors. This will be far easier to build!

Here's an example from my old catalog:

Wide range adjustable triangle oscillator

Notice the hysteretic comparator (top 2N4403's square output fed back to the right side input). The entire left half of this is dedicated to current source/sink to get a symmetrical triangle waveform into the capacitor. A JFET buffer has low leakage for widest range -- this ran something like 1Hz(!) to 4.5MHz in a single range (Ct = 680pF), and up to 30-40MHz flat out (Ct=0, max Freq setting). (At a fixed frequency, probably an emitter follower will do, if any is needed at all.)

  • You might not need the SAW buffer, since it's only going into another comparator, I think? Note that, with less gain in the comparators (single diff pair, no Darlingtons), the extra input bias current (and its change as threshold is approached) may make it worthwhile anyway; or the capacitance and charging bias can simply be increased to "swamp out" those effects. It's a tradeoff.
  • Why simulate the LV supply as well? Note that the 12VAC (RMS) source gives 16V DC, not the 12 implied by the label(!).
  • Note that AC_WAVEFORM can simply be tapped off the boost input (L1/D3/FWB node).
  • What the heck is L2 doing there? It seems to be needlessly increasing M2's peak turn-off voltage, and with such strong drive to it, that's a huge problem. Also D3 is an incorrect choice: SiC diodes are rated for very little surge and a Si PN type is needed here. Or just left out entirely for the simulation (start C1, C12 at some initial voltage to bypass the inrush and startup transient conditions).

Now for the more important things, control:

  • Overall architecture seems to be a boost PFC, with voltage mode control, peak current limiting, and hysteretic voltage regulation. Which... is an unconventional mix, to say the least.
  1. Note that a boost regulator is not linear in duty cycle. That is, its input current goes as, well -- several things, depending on input and output voltage, load current, and load capacitance. In fact the last thing it is, is linearly dependent on Iin(D) -- this is NOT an easy parameter to base the control on!

And indeed, the envelope seems to be heavily distorted, with a double-peaked shape apparently (assuming I'm not seeing just switching noise here -- simulation output can be hard to read like that).

  1. The peak current limiting only pulls in during startup, by the looks of it. Which, fair enough I guess, but -- if you're going to the trouble of sensing current -- and you're trying to regulate input current -- maybe we could do something with that, all of the time, eh?
  2. Hysteretic voltage control means, depending on load demand, input current is just chopping on and off anyway. So the PF over any reasonable time frame, will be pretty poor, and largely dependent on what the load is doing. There is some justification for this: to avoid long startup/overshoot transients, the control probably should respond a bit more promptly than it would otherwise (i.e. in a completely linear control). But it should still be linear for the most part, i.e. for modest variations in load current, and only nonlinear (switching on/off suddenly) for large changes in load current.

Such behavior is usually implemented with a compensated error amp (rolling off at a few Hz, so it doesn't try to regulate against output ripple -- that ripple is necessary for the PFC to function!), with over/under voltage limits to cut off / boost the inverter operation at those extremes. It might also be implemented with a nonlinear transfer function in the error amp (low gm for low inputs say +/-100mV, 5-10x higher gm for larger inputs), so simply as error increases, control speeds up to reign it in faster. (I'm not a fan of the nonlinear amp, myself; it often leads to chaotic instability when the compensation is just a little off, making it difficult to tune in development.)

So, for these reasons, the usual design is a (very slow) voltage error amp, which controls the input current setpoint of the inverter section. This controls the average current, over multiple line cycles. Its output is then multiplied by instantaneous Vin, thus we get a current setpoint that is proportional to Vin in the near term, but the average magnitude is adjusted to regulate output voltage. Finally, the current setpoint controls the inverter, in whatever manner is needed; easiest is probably an average current mode control, feeding back on input/inductor current, and adjusting PWM to suit.

The downsides to this method are: poor compensation (typically a division function block is also used, so that the voltage error amp's output doesn't also depend on average Vin(rms) -- we want to factor that out of the multiplier, again so that it's only multiplying by the instantaneous waveform); poor operation around DCM (discontinuous conduction mode, inductor current falling to zero for part of the cycle); and whatever tradeoffs for operating frequency, component size, etc. (CCM converters need relatively large inductors, which can be affordable powdered-iron types as a result, but are fairly bulky, and not particularly low loss).

There are two other common control methods, which I will describe in order, so as to suggest an evolution between them.

One is BCM (boundary conduction mode, I_L just reaching zero every cycle). Observe that, if inductor voltage is always switched between Vin and Vin-Vout (square waved), and if current exactly returns to zero before turn-on, then average input current is exactly half the peak inductor current, and we can set turn-off by a comparator to that (i.e., a low-side sense resistor, as your R36 and related circuitry). And we can set turn-on by monitoring the inductor voltage and seeing when it falls (D1 turn off). The exact operating frequency might not be known -- it can, and indeed must, vary -- but as long as it's within a reasonable range, we don't care. This simplifies the current feedback loop, to a peak current mode control rather than an error amp. Downside: we still need the multiplier and voltage error amp. And multipliers are HARD to make, reliably and cheaply, whether in discrete or IC form. (Indeed, in ICs they often go to the trouble of digitizing the signal and using some number of bits as a crude multiplier or MDAC, it's that annoying of a problem!)

The last control makes a seemingly small adjustment to the above: what if, instead of turning off at some peak current, we turn off after some given on-time? Scary: we don't know what input current is, at all (at least, not on a cycle-to-cycle basis). This runs counter to the logic of a current-mode control: we lose the safety granted by controlling the switching current. Maybe under adverse conditions (typically startup and load-fault) it could blow up, and we need to figure out contingencies to deal with that. Well, let's see where it goes.

If we're doing some fixed on-time, then the inductor always charges with some energy proportional to supply voltage.


That means we can remove the multiplier block, doesn't it? HMMMMM.

And then the voltage error amp simply varies on-time to maintain average DC output.

In fact the input current is given by: $$ I_\textrm{in} = \frac{V_\textrm{in} t_\textrm{on} \left( V_\textrm{out} - V_\textrm{in} \right) }{2 L V_\textrm{out}} $$ so it's linear in t_on, and mostly linear in V_in (I mean, it's actually quadratic, but over a modest working range, the gain error won't be so bad that we can't compensate the error amp).

So the circuit reduces to a voltage error amp and a one-shot timer. It oscillates by, effectively, the ping-pong between internal timer, and the one-shot effected by the inductor current falling to zero. And the latter is very easy to sense (the large signal of switch-node voltage falling below Vin; or, more often, by a sense winding on the inductor, its zero crossing).

The main downsides to this are, we still need some way to control current during startup/fault conditions (we could OR the timer with the current comparator signal), and, operation sucks at low V_in: notice the switch node will always have some capacitance on it, therefore some inductor energy is lost simply to charging that capacitance, and more is lost when the voltage swing is higher, so, in short: input current drops at low input voltage, and low output current. Thus, we expect relatively high crossover distortion (at the line input current), with poorer operation at light load. (Typical controllers of this type, use a hysteretic mode at light load, so they draw input current in bursts -- the bursts still having good power factor, though.)

More inspiration: https://www.glensstuff.com/videopong/videopong.htm

This guy is... kind of crazy, in committing to build all of that. A fantastic bit of work.

  • \$\begingroup\$ Now that I'm well rested, I'd like to pick your brain a little if you don't mind. Let's start with a stupid question: I did some research on BJT multipliers, which only lead to confusion. Which is the multiplier block in the circuit? My guess is the 120Hz arc signal that I feed into PWM's + (non inverting) input. Is that correct? \$\endgroup\$
    – user14828
    May 19 at 18:02
  • \$\begingroup\$ I also got rid of the SiC diode and replaced it with a Si PN which greatly improved the performance. I hadn't looked up the datasheet. I will be using an SiC (FFSH40120N) diode to rectify the output voltage though. The problem now is that, like most boost converters, it only boosts to 318V with a load. I'm still trying to figure that part out. It's at a fixed frequency of 148KHz, so I'm thinking to set a fixed, high duty cycle and let the current error amplifier control the duty cycle. Something like an always on current mode buck converter a designed a while back that worked well in sim \$\endgroup\$
    – user14828
    May 19 at 19:17
  • \$\begingroup\$ How does it look now in comparison to the original? It seems to be working okay. It reaches steady state at >120ms. \$\endgroup\$
    – user14828
    May 19 at 23:55
  • \$\begingroup\$ Oh and thanks on the info on the Darlingtons. I usually don't go that route, I just figured for PFC it should be how the chips are made. Grounding and having to jump over them would be a pain in the a**. Being the waveforms are looking okay and I'm getting the output voltage I wanted, I'm gonna go for a build. Wish me luck! FYI, I also designed a BJT version of the KA3525A, using an astable mulivibrator, with all of the bell and whistles, that I've tested and works. Just had to go with resistors to charge the caps because CCS wouldn't work because of inconsistencies in the BJT matching. \$\endgroup\$
    – user14828
    May 20 at 3:26

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