# DRAM Refresh Time

I am trying to understand, how can I calculate the refresh time of DRAM, if I consider that as my memory requirement, that I need is 32 DRAM chip of 1M * 1bit each to get 4MB Memory capacity. Each DRAM chip has 1k rows, and each row has 1k cells. If I consider each refresh cycle takes 100ns. So basically I have confusion in two approaches:

(I) Considering Refresh time as per each Chip: So, as we know DRAM refreshes single row at a time, each row has 1k cells, in total DRAM chip has 1k * 1K cells, as each row refreshes in 100 ns, I consider it as 1k*100ns. finally as we need 32 such chips so final refreshing time will be 32 * 100 * 1k(2^10).

(II) Another way i look to this problem is, If all chip are connected in series, that means all 32 chips, its row are in line, so that means total refresh time will be equal to that of only one chip refresh time. i.e. 100ns * 1k(2^10).

So, which scenario is considered to be standard one?

• Please provide a link to the manufacturer's datasheet for the DRAM in question. May 18, 2022 at 15:06
• You can refresh multiple chips in parallel. I have no idea what you mean by connecting them in series.
– user16324
May 18, 2022 at 15:50
• Hi @user_1818839 actually the question arises, how to arrange these 32 chips as there can be many possible arrangements. There is a logical arrangement provided in the problem statement itself as “1M x 1 bit chip”. This indicates that to make a “1M x 32 bits” MM, we need to arrange all 32 chips in a line. It is to be noted that a row in all chips in series can be refreshed in one refresh cycle. From this statement i am confused, is this arrangement of chip valid? May 19, 2022 at 2:45
• Still no idea what exactly you mean with series DRAM, OP, but whatever it is, since refresh rate is just a software thing (if you wire everything correctly), you can try various ways and see what happens, just write some 0x01 0x02...0xFF 0x01 0x02 0x03... into memory and read it back after some time. After all, this refresh period is just a number in software. If you try it, make sure you share your findings with us.
– Ilya
May 19, 2022 at 8:06
• In a comment you are describing all 32 devices in parallel. Series would mean one chip was feeding the next which makes no sense. So refresh them in parallel, and control the refresh timing parameters as per the datasheet.
– user16324
May 19, 2022 at 9:33