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I am trying to understand, how can I calculate the refresh time of DRAM, if I consider that as my memory requirement, that I need is 32 DRAM chip of 1M * 1bit each to get 4MB Memory capacity. Each DRAM chip has 1k rows, and each row has 1k cells. If I consider each refresh cycle takes 100ns. So basically I have confusion in two approaches:

(I) Considering Refresh time as per each Chip: So, as we know DRAM refreshes single row at a time, each row has 1k cells, in total DRAM chip has 1k * 1K cells, as each row refreshes in 100 ns, I consider it as 1k*100ns. finally as we need 32 such chips so final refreshing time will be 32 * 100 * 1k(2^10).

(II) Another way i look to this problem is, If all chip are connected in series, that means all 32 chips, its row are in line, so that means total refresh time will be equal to that of only one chip refresh time. i.e. 100ns * 1k(2^10).

So, which scenario is considered to be standard one?

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  • \$\begingroup\$ Please provide a link to the manufacturer's datasheet for the DRAM in question. \$\endgroup\$ May 18, 2022 at 15:06
  • \$\begingroup\$ You can refresh multiple chips in parallel. I have no idea what you mean by connecting them in series. \$\endgroup\$
    – user16324
    May 18, 2022 at 15:50
  • \$\begingroup\$ Hi @user_1818839 actually the question arises, how to arrange these 32 chips as there can be many possible arrangements. There is a logical arrangement provided in the problem statement itself as “1M x 1 bit chip”. This indicates that to make a “1M x 32 bits” MM, we need to arrange all 32 chips in a line. It is to be noted that a row in all chips in series can be refreshed in one refresh cycle. From this statement i am confused, is this arrangement of chip valid? \$\endgroup\$
    – Niraj Jain
    May 19, 2022 at 2:45
  • \$\begingroup\$ Still no idea what exactly you mean with series DRAM, OP, but whatever it is, since refresh rate is just a software thing (if you wire everything correctly), you can try various ways and see what happens, just write some 0x01 0x02...0xFF 0x01 0x02 0x03... into memory and read it back after some time. After all, this refresh period is just a number in software. If you try it, make sure you share your findings with us. \$\endgroup\$
    – Ilya
    May 19, 2022 at 8:06
  • \$\begingroup\$ In a comment you are describing all 32 devices in parallel. Series would mean one chip was feeding the next which makes no sense. So refresh them in parallel, and control the refresh timing parameters as per the datasheet. \$\endgroup\$
    – user16324
    May 19, 2022 at 9:33

1 Answer 1

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There are two extreme ways to use those 32 DRAM chips. (Actually there are 6 ways, but let's take a look only those extreme cases.)

  1. Place 32 chips in parallel. In other words, the whole architecture looks like 1M x 32bits. You write and read minimum 32b data. In this case, a refresh command is applied to all those 32 chips simultaneously. Assuming that a cell needs to be refreshed every 10ms for simplicity (actually this is 32ms, 64ms or 128ms), you have to refresh each row once every 10ms. As the whole architecture looks like 1K rows X 32Kb/row, you have to issue 1K refresh commands every 10ms. This locks up the memory for 100ns X 1K = 100us, so the refresh penalty is 1% (100us / 10ms).

  2. Dot (short) the data bit of 32 chips altogether. If you draw this configuration, it will look like all those 32 chips are placed vertically (in contrast to 'horizontally' in the case-1). At least chip selects or some ID bits should be separate for all those 32 chips, because all those DRAM chips will be accessed sequentially. I guess this may be why you described it as 'in series'. Anyway, the whole architecture looks like 32M x 1bit. You write and read 1b at a time. In this case, a refresh command is applied to only 1 chip at a time. Again assuming that a cell needs to be refreshed every 10ms for simplicity, you have to refresh each row once every 10ms. As the whole architecture looks like 32K rows X 1Kb/row, you have to issue 32K refresh commands every 10ms. However, while one chip is refreshing, you could still access other 31 chips. So the lock up time due to refresh may be hidden, but on average still 1/32 of chip is not accessible, so the total effective lock up time is 32K X 100ns X 1/32 = 100us (same to the case-1!).

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