I'm trimming off some parts from an eval board schematic, and I'm not sure what the purpose of this dual-facing diode / rectifier is.

The voltage divider from R33 and R48 is scales by a factor of 10 or so (i.e. for VBUS_USB the voltage at pin 3 of the rectifier would be 0.5V when VBUS_USB is at 5V and 2.0V when the VBUS_USB is at 20V, which is the expected range of voltages on the bus.)

enter image description here

I'm guessing this is some sort of protection. Note the original schematics show this pin 3 to be connected to some op-amp setup measuring discrete voltage levels on V_BUS so maybe this is relevant. The original schematics are linked above. I didn't need to measure these discrete voltages in my end product so I cut the op-amp circuit out.

Also maybe relevant is the pin description from the UPD301C datasheet for VBUS_DET_IN:

Scaled down version of VBUS input used for VBUS detection. Tie this signal to VBUS via a resistor divider. (VBUS_DET in UPD350)

Thinking it through:

  1. If pin 3 is normally around 0.5V, both diodes would normally be off (open circuit).
  2. If the 3v3 output from the LDO (MCP1804) dropped below 0.5V the top diode would start conducting, though I'm not sure why this would be a good thing.
  3. If VBUS_USB dropped below some voltage, and pin 3 dropped to zero, we're in the same scenario as 1.
  4. If VBUS_USB spiked from some transient such that pin 3 went above 3.3V, the top diode would start conducting, but wouldn't this then pit the LDO against the spike and potentially damage the LDO?

I'm also not sure what the capacitor is doing there, but guessing it is protecting against some sort of transients along with the diodes from case 4. above.

If anyone has a good explanation or can simply point me to a reference or name for this kind of protection, I'd be happy to read up on it more.

  • 1
    \$\begingroup\$ Spikes are current-limited because of R33. It's unlikely that enough current will get through R33->D16->3.3V to cause a problem. Mostly it will have the effect of limiting the signal voltage. \$\endgroup\$
    – user253751
    May 19, 2022 at 9:03

2 Answers 2


The idea is to protect pin 9 of U4 from high voltage or negative voltage on VBUS_USB.

VBUS USB goes to something outside of the circuit board. Since it is a USB C power source, it could legitimately have up to 19V on it.

Bad things can happen, though, so that you could end up with more than 19V on that pin - or a negative voltage.

R33 and R43 form a voltage divider to reduce the expected 19V to a maximum of 1.9V.

If the voltage at the junction of R33 and R34 goes above about 3.4V, then one of the diodes clamps the voltage to 3V3.

If the voltage at the junction of R33 and R34 goes below about -0.1V, then the other diode clamps the voltage to 0V.

Both protect the input of U4.

Since VBUS_USB has to go through R33, the current through the diodes will be very low - no danger to the power rails.

  • \$\begingroup\$ they don't quite clamp the pin voltage to 3.3V and 0.0V. But they clamp the overvoltage amount to about 300 mV both ways which is low enough that the clamping diodes inside the IC do not conduct appreciably. \$\endgroup\$
    – tobalt
    May 19, 2022 at 10:41
  • \$\begingroup\$ Can you comment on how realistic/probable it would be to have a commercial USB plug VBUS enter either of these regions? (i.e. negative, or over 33V?). I'm happy leaving the thing there as it is pretty small compared to the other things I'm cutting out, but just curious if you've seen this actually happen as it seems quite extreme, but I'm rarely hooking up my USB sources to the scope! :D \$\endgroup\$
    – topher217
    May 19, 2022 at 12:29
  • \$\begingroup\$ It isn't just the power supply. Merely touching the connector while electrostatically charged can cause high voltages on VBUS. You know that annoying "Zap" when you walk across a carpet and touch something? That's electrostatic discharge. \$\endgroup\$
    – JRE
    May 19, 2022 at 12:34

One could make the argument that it's unnecessary, yes.

It is a clamping diode, as mentioned by others. Note that BAV99 has a fairly high Vf, so that the MCU's input clamping (ESD) diodes are likely to be forward-biased as well -- they're basically in parallel, and so will share some undefined amount of current. We normally also prefer putting a series resistor (before the MCU pin) so that the current sharing is better defined: take Vf(max) at Ipk, subtract pin Vf (rarely documented; assume 0.6V), divide by pin Imax (e.g. 5mA), and this gives the resistance required to limit current safely.

This is ignoring particulars about what the chip is, what it's doing, etc.

If it's an MCU, likely the pin is an analog input, with Imax = 0 for normal operation; we need a better clamping strategy in that case. We could use schottky diodes (e.g. BAT54S), or a more complicated clamping arrangement.

Checking, I see UPD301C is a power management chip, and as evident from the pin name, it's likely special function, and may have a different ESD solution. Indeed, the datasheet says on p.30:

UPD301B/C Stand-alone USB Type-C Power Delivery 3.0 Controller

Maximum 4V (well, 3.96V; that's a very peculiar choice..). Note it is independent of supply voltage (contrast with the other pins being relative to VDD33_REG_IN), meaning they must have some kind of zener or snapback diode, not a clamp diode to VDD.

But we can go further. Also as mentioned by others, the only likely concern is ESD. (Cross-wiring would be the only other option, and pretty hard to do with USB connectors I would think!?) ESD is a very high voltage (8kV or even more), but it's a very brief pulse (~50ns) from a fairly modest source (1.5kohm, give or take which standard you're using). So, the peak current is quite high (>10A) during that pulse, but not a whole lot of charge is delivered.

So we can use the 3V3 supply for clamping, as long as it has adequate capacitance. C33, C19, and there are probably many others in the circuit as well, all act in parallel. A few uF is enough to get the peak voltage in a reasonable range.

But further: C18, C20 and maybe others already provide this service at the VBUS node itself. So any ESD seen by VBUS_DET_IN is likely very small indeed!

There is a final surge condition that can occur: when the input rises very sharply (and with little current limiting), the cable inductance can resonate with the input capacitance (C18, C20, etc.), doubling (or more!) the peak voltage.

Note this requires \$I_{in(pk)} \sim \frac{V_{bus}}{\sqrt{\frac{L}{C}}}\$, for L the cable inductance (ballpark 0.3uH/m), C the total bypass, and Vbus the nominal supply voltage (with the capacitors being initially discharged).

A simple solution is some lossy capacitance on VBUS (an electrolytic several times the total (ceramic) capacitance), or a TVS to clamp the peak voltage not much higher than nominal.

(The RLC series resonant circuit, has a step response of peak exactly twice the input. How could it be more? Ceramic capacitors: the capacitance drops as voltage rises. The C(V) curve is not flat as we would like, but substantially depressed. As the inductor charges to peak current, and VBUS charges past nominal, C drops precipitously, thus the inductance is effectively over-charged relative to the new value of capacitance -- voltage thus rises even faster, and shoots up to a peak easily 3x or higher. I recommend choosing ceramic caps only where you can see the C(V) characteristic curve, and selecting them to retain say 70% of nominal capacitance, at nominal voltage. Probably a 2.2uF would have to be 1206 sized or larger to meet this.)

Note that U3's limit is 30V as well, so this would be relevant under the necessary circumstances, and maybe other things off screen too.

Note, this probably should not happen with normal USB-C sources (with negotiated power, and limited peak current and slew rate).

On a completely different note, the grounding is insufficient. If EARTH_P1 must be kept separate, I would insist on at least four bypass caps in parallel, positioned around the connector, as close as possible to the pins/pads. If not separate, just hard-ground it to the internal ground plane.

ESD is most likely of all to strike the shield, dropping a huge voltage across this poor capacitor (100s of V -- the cap, traces and pins will total maybe 5nH, and the risetime is merely a few ns!), and thus disturbing the CCx and D+/- pins by as much (and RX/TX lanes, if they were in use). (This probably won't phase the, whatever's connected to the pins respectively -- this will be not much worse impedance than regular ESD, but at a much lower voltage, so much less energy/charge. It could still cause malfunction (corrupted data) or require a power cycle.)

This is also an RFI immunity concern.

(I'm not clear on if this is a design or review question, so take this as directed at readers interested in more of the design aspects.)

  • \$\begingroup\$ Very thorough Tim! I did not place the separate EARTH_P1, and superficially understand your point, but I'm curious what the counter argument to yours would be (i.e. why should the shield be kept separate?) \$\endgroup\$
    – topher217
    May 20, 2022 at 2:42
  • 1
    \$\begingroup\$ Good question -- the shield might be separated when using a metal enclosure, like ports on a PC. The circuit ground might not be quite equal to chassis ground, some isolation being desirable; and with an EMI gasket between connector and chassis, ESD is diverted away from the port, so we don't need especially good shielding to the board. This is contingent on the CM noise between chassis and circuit being small. \$\endgroup\$ May 20, 2022 at 15:31

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