I'm trying to understand Backdoor Access within UVM RAL mode example https://www.edaplayground.com/x/jy3U .

In uvm_guide, it wrote that if HDL paths are used, the root HDL paths must be specified in the environment that instantiates the register model.

I implemented reg_model.set_hdl_path_root("tb_top.DUT"); in env.sv and control_reg.configure(this, null,"control_reg"); in reg_pkg.sv

Then I implemented it to test Backdoor access in base_seq.sv.

    `uvm_info(get_type_name(), "BACKDOOR ACCESS START", UVM_LOW);
    reg_model.mod_reg.control_reg.write(status, 32'h9876_5432, UVM_BACKDOOR, .parent(this));
    reg_model.mod_reg.control_reg.read(status, read_data, UVM_BACKDOOR, .parent(this));
    `uvm_info(get_type_name(), "BACKDOOR ACCESS FINISH", UVM_LOW); 

I didn't get any Backdoor operation message between BACKDOOR ACCESS START and BACKDOOR ACCESS FINISH.

Could you guide me how I can setup the Backdoor access?


1 Answer 1


To see more messages, you need to change the verbosity setting. When you don't explcitly set the verbosity, UVM_MEDIUM is used. On edaplayground, change Run options from:

-access +rw



This is what I see when I run it:

UVM_INFO base_seq.sv(35) @ 14: uvm_test_top.env_o.agt.seqr@@rseq [reg_seq] BACKDOOR ACCESS START
UVM_INFO @ 14: reporter [RegModel] Wrote register via DPI backdoor: reg_model.mod_reg.control_reg=0x12341232
UVM_INFO @ 14: reporter [RegModel] Read  register via DPI backdoor: reg_model.mod_reg.control_reg=12341232
UVM_INFO base_seq.sv(38) @ 14: uvm_test_top.env_o.agt.seqr@@rseq [reg_seq] BACKDOOR ACCESS FINISH

You can also use UVM_FULL or UVM_DEBUG.


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