I've developed a domino circuit which calculate a simple logic function.


I would like to latch the output "sum" into registers for further use. At the moment the logic goes to 0 during precharge as it should in domino logic. I want to latch this output without violating the hold time.


2 Answers 2


You don't provide a schematic, so the best I can do is to show you ONE example of how to incorporate a latch.


simulate this circuit – Schematic created using CircuitLab


I have no idea what a domino circuit is so i'll be stupid and assume that the waveform you have shown you want delaying by 1/2 pulse. Do you have a clock running that has positive transitions in the middle of the positive pulses? If you do then use a simple D type latch with the clock fed to the clock input and the data (as shown on the picture) going to the D input. The Q output will be delayed by half of one pulse. Does this then give you enough time to latch V(sum)?

I've probabaly missed the point here and if I have please ignore my ramblings or downvote (with explanation to enable me to learn) as you see fit

  • \$\begingroup\$ You got the solution right, but the thing is that I have no clock half a cycle apart. So my question is, whats the method to latch the output using only the available clock? \$\endgroup\$
    – Codename
    Mar 23, 2013 at 18:02
  • \$\begingroup\$ @Dez you could fairly easily use an analogue delay on the existing clock. Use an RC filter and a schmidtt trigger circuit to give-back a decent logic shaped signal. This could easily produce a clock that looks like the original clock but delayed by up to 1/4 cycle - would this be enough time to do what you need? Else, use a monostable on the clock signal that produces an output that's 25% on and 75% off; use the logic 1 to logic 0 edge to latch the signal? \$\endgroup\$
    – Andy aka
    Mar 23, 2013 at 18:39

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