Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.
Sign up to join this community
I've developed a domino circuit which calculate a simple logic function.
I would like to latch the output "sum" into registers for further use. At the moment the logic goes to 0 during precharge as it should in domino logic. I want to latch this output without violating the hold time.
You don't provide a schematic, so the best I can do is to show you ONE example of how to incorporate a latch.
simulate this circuit – Schematic created using CircuitLab
I have no idea what a domino circuit is so i'll be stupid and assume that the waveform you have shown you want delaying by 1/2 pulse. Do you have a clock running that has positive transitions in the middle of the positive pulses? If you do then use a simple D type latch with the clock fed to the clock input and the data (as shown on the picture) going to the D input. The Q output will be delayed by half of one pulse. Does this then give you enough time to latch V(sum)?
I've probabaly missed the point here and if I have please ignore my ramblings or downvote (with explanation to enable me to learn) as you see fit
