I'm currently designing an SMPS buck converter that converts 311VDC to 60VDC at 10 Amps maximum load. I'm using ESP32 for the PWM control, and IR2110 for the switching driver. The switch I'm currently using is an NMOS (STW45NM60) that's placed at the high side of the circuit. The circuit I'm using can be seen in Fig 1 and Fig 2 below. For your information, I've asked about my circuit on this forum before, here and here. I think that the question I'm about to ask is different from my last question to warrant a new post.
Now the problem is, even though the NMOS is rated at 40A and 600V, it rapidly heats up when the average current output is only 800mA. I then try to measure the current waveform in the drain and source (with a current probe), and it turns out that there are huge current spikes happening both in the drain, and the source of my NMOS. The drain spike can be seen in Fig 3 below.
Fig 3. Current spike in drain. I forgot the input and average output current for this corresponding current waveform. But when I give 30VAC as the input, the average current output is 238mA, and the spikes reached up to 1500mA. The spikes is the same as the picture above. I measured the current spike with a current clamp probe.
I've tried adding an RLD snubber network after the NMOS source (between Nodes B and C in Fig 2) and the current spikes seems to not be reduced as much. And another thing I need to mention is that when I put the RLD snubber in my circuit, the gate-source voltage is no longer 12V (it increases as the input voltage increases). I'm afraid this may cause damage to my NMOS (as the VGS rating is only 20V). In Fig 4, you see where exactly I put the RLD network in my circuit
Fig 5. VGS without RLD (left) and VGS with RLD (right). Apologies, I edited the right waveform's cursor value because I didn't take a picture of VGS without the RLD circuit. I just want to inform that the VGS waveform (with or without RLD) is still the same, but the amplitude's different.
Besides the spiking issue, there's also a minor problem (I don't know whether this is a problem or not, but I'm a little bit concerned about this) in the VGS waveform. If I apply a high enough AC voltage in my input (I'm using an adjustable AC transformer for the input), there's a voltage spike and ringing that appears in the VGS waveform, specifically when the waveform changes from HIGH to LOW. These spike and ringing is present with or without the RLD network. You can see the spike and ringing in Fig 6 below
Fig 6. Voltage spike and ringing at VGS. ON voltage is 11V. You can see that the spike can reach up to -7V, and the ringing is at 25MHz. I'm afraid that this will cause damage to the NMOS.
EDIT: After typing this question, I tried putting the RLD network before the MOSFET. With R = 40Ω, and L = 1mH, the current spikes is lowered, but not significantly. But at least, the VGS doesn't change in amplitude like in Fig 5 (right side). The circuit for this setup can be seen in Fig 7, my measurements for said circuit can be seen in Fig 8, and as someone requested in the comments, the source-ground waveform can be seen in Fig 9.
Fig 8. Measurements for fig 7
So my question would be
- Is there something wrong with my RLD snubber (placement or topology) that causes the VGS to go up as the input voltage increases? [SOLVED-ish. I moved the RLD snubber to the drain side and VGS is now constant]
- Besides the RLD, is there any other way to mitigate the current spikes?
- Why is there a voltage spike in VGS if the input voltage is high? Is this dangerous for the NMOS and or IR2110?
- Putting the RLD in the drain side seems to not reduce the current spike as much as I wanted, is this because bad RLD placement? Or wrong R and L values?
If it helps, my setup can be seen in Fig 10 below, and the PCB design can be seen in Fig 11. Fig 10. Test setup. Left scope is for current measurement, to prevent stray noises when measuring voltage. VGS measurement is done with the right scope