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I'm currently designing an SMPS buck converter that converts 311VDC to 60VDC at 10 Amps maximum load. I'm using ESP32 for the PWM control, and IR2110 for the switching driver. The switch I'm currently using is an NMOS (STW45NM60) that's placed at the high side of the circuit. The circuit I'm using can be seen in Fig 1 and Fig 2 below. For your information, I've asked about my circuit on this forum before, here and here. I think that the question I'm about to ask is different from my last question to warrant a new post.

Driver circuit Fig 1. NMOS driver circuit

Buck converter circuit Fig 2. Buck converter circuit

Now the problem is, even though the NMOS is rated at 40A and 600V, it rapidly heats up when the average current output is only 800mA. I then try to measure the current waveform in the drain and source (with a current probe), and it turns out that there are huge current spikes happening both in the drain, and the source of my NMOS. The drain spike can be seen in Fig 3 below.

Current spike in drain

Fig 3. Current spike in drain. I forgot the input and average output current for this corresponding current waveform. But when I give 30VAC as the input, the average current output is 238mA, and the spikes reached up to 1500mA. The spikes is the same as the picture above. I measured the current spike with a current clamp probe.

I've tried adding an RLD snubber network after the NMOS source (between Nodes B and C in Fig 2) and the current spikes seems to not be reduced as much. And another thing I need to mention is that when I put the RLD snubber in my circuit, the gate-source voltage is no longer 12V (it increases as the input voltage increases). I'm afraid this may cause damage to my NMOS (as the VGS rating is only 20V). In Fig 4, you see where exactly I put the RLD network in my circuit

Buck converter circuit with RLD network Fig 4. Buck converter circuit with RLD network

enter image description here Fig 5. VGS without RLD (left) and VGS with RLD (right). Apologies, I edited the right waveform's cursor value because I didn't take a picture of VGS without the RLD circuit. I just want to inform that the VGS waveform (with or without RLD) is still the same, but the amplitude's different.

Besides the spiking issue, there's also a minor problem (I don't know whether this is a problem or not, but I'm a little bit concerned about this) in the VGS waveform. If I apply a high enough AC voltage in my input (I'm using an adjustable AC transformer for the input), there's a voltage spike and ringing that appears in the VGS waveform, specifically when the waveform changes from HIGH to LOW. These spike and ringing is present with or without the RLD network. You can see the spike and ringing in Fig 6 below

enter image description here

Fig 6. Voltage spike and ringing at VGS. ON voltage is 11V. You can see that the spike can reach up to -7V, and the ringing is at 25MHz. I'm afraid that this will cause damage to the NMOS.

EDIT: After typing this question, I tried putting the RLD network before the MOSFET. With R = 40Ω, and L = 1mH, the current spikes is lowered, but not significantly. But at least, the VGS doesn't change in amplitude like in Fig 5 (right side). The circuit for this setup can be seen in Fig 7, my measurements for said circuit can be seen in Fig 8, and as someone requested in the comments, the source-ground waveform can be seen in Fig 9.

RLD moved to the drain side Fig 7. RLD moved to the drain side

Measurements for fig 7

Fig 8. Measurements for fig 7

Source-GND waveform for fig 7 Fig 9. Source-GND waveform for fig 7. For this waveform, the VAC input is 60V-ish, and there's a voltage spike (and ringing) after every turn ON cycle.

So my question would be

  1. Is there something wrong with my RLD snubber (placement or topology) that causes the VGS to go up as the input voltage increases? [SOLVED-ish. I moved the RLD snubber to the drain side and VGS is now constant]
  2. Besides the RLD, is there any other way to mitigate the current spikes?
  3. Why is there a voltage spike in VGS if the input voltage is high? Is this dangerous for the NMOS and or IR2110?
  4. Putting the RLD in the drain side seems to not reduce the current spike as much as I wanted, is this because bad RLD placement? Or wrong R and L values?

If it helps, my setup can be seen in Fig 10 below, and the PCB design can be seen in Fig 11. Test setup Fig 10. Test setup. Left scope is for current measurement, to prevent stray noises when measuring voltage. VGS measurement is done with the right scope

PCB design Fig 11. PCB design. There's a lot of terminal blocks so that testing snubbers can be easier

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    \$\begingroup\$ Where did you get your inductor from? If it is saturating, then you’ll get current peaks. According to the scope pics, you’re running around 40% duty cycle - what is your load? \$\endgroup\$
    – Kartman
    Commented May 20, 2022 at 6:13
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    \$\begingroup\$ My load is a 50ohm resistor. If it is saturating, then you’ll get current peaks. Which inductor did you mean? \$\endgroup\$
    – Kevin
    Commented May 20, 2022 at 6:19
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    \$\begingroup\$ Pcb layout needs attention. Ir2110 has no bypass cap on it. Remember every wire is an inductor - and you have plenty of them including your current sense loop. And why use an esp32 with its crappy adc for psu control? You’re making your task harder. \$\endgroup\$
    – Kartman
    Commented May 20, 2022 at 6:21
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    \$\begingroup\$ Looks like inductor saturation + poor layout causing ground bounce. \$\endgroup\$
    – winny
    Commented May 20, 2022 at 6:22
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    \$\begingroup\$ @Kevin - Hi, Regarding: "I think that the question I'm about to ask is different from my last question to warrant a new post." This is an issue when someone has an "evolving" problem. We now have three overlapping "open" questions (i.e. without a clear conclusion and an accepted answer (or otherwise closed)) for the same project of yours. Someone may notice question X and spend time on the old/obsolete info there, not realising that you've moved onto question Y and now even Z. Please review your previous questions & see if they can be closed. Are they still needed? If so, why? Thoughts? \$\endgroup\$
    – SamGibson
    Commented May 20, 2022 at 8:11

1 Answer 1

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Your inductor is saturating.

It appears you are using a green toroidal inductor with only a handful of turns. Any magnetic core that is able to achieve 1mH of inductance with so few turns has very high magnetic permeability. That means that while you can achieve a lot of inductance with relatively few turns, that inductance will saturate at very low currents. There is no way that inductor will handle hundreds of mA, nonetheless 10A.

Green toroid cores like that are typically used to make common mode chokes for EMI suppression. Common mode chokes use two windings with current flowing in opposite directions whose magnetic fields mostly cancel each other out. That means while the inductance is high, the core is subjected to a very weak magnetic field and that is all it is meant to withstand. Such cores are totally unsuitable for power conversion where large DC biases and stronger fields will be present. Simply put, they will not work for your application.

The wire certainly looks like it can handle 10A - so I suspect you chose your inductor based on the maximum DC current spec and not the saturation current. The maximum DC current is determined mainly by the winding wire resistance and size. It doesn't imply anything about if your inductor will even be much of an inductor at that current or not though.

Saturation current is the current at which your inductor has lost 20% of its inductance. Unfortunately, ferrite-based core materials (like those green toroids) do not saturate linearly. They saturate like jello hitting a brick wall at mach 1. Going over the saturation current results in a sharp decrease of the inductor's inductance, essentially approaching what that inductance would be with an air core instead of a magnetic one.

You should understand that ideally you want 30-40% ripple current (an AC current wave form superimposed on the output current through the inductor. This also means you need 1.4 times your output current worth of saturation current, so 14A.)

Ripple current is easily calculated: \$ I_{ripple}= \frac{V_{out}\left (1 - \frac{V_{out}}{V_{in}} \right )}{Lf_{sw}} \$ where L is the inductance and f is the switching frequency.

For your application, that would correspond to about 200uH. There is no advantage to using an inductor as large as you are using, and a 1mH inductor that can withstand 14A of saturation current is impractically large. Even 200uA at 14A is quite big, but such inductors do exist and can be found on Digi-Key.

You may want to consider doubling your switching frequency, as this would reduce the needed inductance in half, albeit at the cost of higher losses in your MOSFET.

Also, snubbers limit voltage spikes, not current spikes. You use them to prevent a voltage spike blowing a hole through a MOSFET's thin and relatively fragile oxide insulating layer.

So there is nothing wrong with your snubber topology - it is just that they won't do anything helpful with regard to current spikes. The only thing that limits current is series resistance (or reactance, or both aka impedance, which you are losing far too much of due to inductor saturation).

As for gate ringing and drain to source spikes, that is the cost of doing business with a MOSFET. They turn on fast and hard and parasitics conspire to form a resonant LC tank on the switch node while parasitic inductance between the gate and drain forms a series resonant tank that gets actively amplified (since it is controlling the gate somewhat) and briefly the MOSFET turns into an active colpitts oscillator. There is already an excellent answer on this that is worth checking out, so I'll not go too deep into it myself.

There are several things you need to do to combat this:

  1. Reduce the parasitic inductance. In the context of a buck converter, this means your input capacitors need to be as physically close to the MOSFET drain as possible. And I mean every millimeter distance will make the ringing noticeably worse. Using a TO-220 will make it worse just because of the lead inductance. You want some nice fat ceramic capacitors basically soldered directly between the drain and ground, and keep that entire loop (including ground) as physically small as possible.

  2. Don't turn the poor FET on so hard. Put a small gate resistor in series with the gate. A few ohms will be a good place to start. This will slow the turn on transition of the FET and cause more switching losses, but will reduce the ringing which will reduce losses from that. It is a bit of a trade-off. Well, unless the FCC is on your butt. Then you just make the ringing below a certain amplitude no matter what the cost.

  3. Use snubbers correctly. This is what they will help with - voltage spikes due to ringing. This is where you can play around with snubber topologies and values - just connect them across the source and drain of the MOSFET. They will reduce the amplitude and frequency of the ringing but at the cost of more power dissipation. The more effective a snubber is, the more power it is eating up. You can get really fancy here though or even explore things like active snubbers if you want.

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  • \$\begingroup\$ Thank you for a very detailed answer! I'll try using another core. Although if possible, I would prefer not buying from Digikey, as I'm currently in Indonesia, and the shipping time will take a long time. Can I buy another core with high saturation current and build it myself? Although if that's not possible, I suppose I'll have to bear with the wait \$\endgroup\$
    – Kevin
    Commented May 27, 2022 at 2:56
  • \$\begingroup\$ I would also like to confirm some things. From your answer, what I got is that my RLD snubber can't suppress the current spikes, because the problem lies on my main inductor (L1 in fig 2), so I should ditch the RLD and change L1. Is this true? You also mentioned about putting a gate resistor in series with the gate, is R2 (in Fig 1) considered a gate resistor? Or should I add another resistor after the "PWM_IR" node? And also, "putting the input capacitors as close to MOSFET drain", did you mean the C4 capacitor in Fig 2? \$\endgroup\$
    – Kevin
    Commented May 27, 2022 at 2:58

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