I have the circuit below which consists of a series resistor followed by a parallel LC circuit:
It produces this output waveform:
From the simulation, I know the waveform has a frequency of 10Khz since the period of 1 complete cycle almost 100 microseconds. The parallel LC circuit has a stopband of 10Khz which is to capture the 10Khz signal. Since the carrier id 8MHz, the parallel LC circuit acts a near short circuit to ground so that only a very small constant amplitude of thr carrier signal remains. In FM modulation, there is a series of frequencies in the waveform. The 50ohm and the parallel circuit parallel LC circuit form a voltage divider circuit according to the formula:
$$V_{out}=V_{in}\frac{z}{z+50}$$
Where z is frequency dependent then voltage output also varies with time according to the potential divider formula. The voltage output is the filtered carrier amplitude+Vout of the stopband. This explains why the output voltage is changing with time.
For the second part, I can't find the reason why the amplitude decreases after the simulation is run for a period of time:
Please help to explain or give some hint on this.