What can procedural statements do that assignment statements cannot do in Verilog?

Question

It seems to me that for combinational circuits assignment statements are much better and for sequential as well we can use if(clk) to run programs up to an extent, so what significant advantage does procedural blocks give in comparison to assignment statement?

Answer 1

Adding one more thing to what Dave said:

This works to add a #1 transport delay to a testbench signal.

always_comb
  sig_del <= #1 sig;

This errors:

assign sig_del <= #1 sig;

Answer 2

I assume you are trying to compare a continuous assign statement with procedural assignment inside an always block.

assign A = B;

versus

alway_comb A = B;

In this example, like many other constructs in Verilog, there is overlapping functionality. One of the biggest differences is that only the assign statement can be used to make an assignment to a net/wire. In SystemVerilog, you can use either statement to make assignments to a variable. However you can use one and only one statement to make an assignment to a particular variable.

You would use multiple assign statement to make multiple assignments to the same wire; for example, a bidirectional bus. The procedural assignment in an always block lets you break up expressions into more complex equations and use procedural constructs like for-loops and case statements.

Like a function call, a continuous assignment only targets a single output result. A procedural assignment block can target multiple variables that share common branches, like the items in a case statement.