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In this article, there is a section that models the capacitance of a via.

The equation given is:

$$C=\frac{(0.55\epsilon_rTD_1)}{D_2-D_1}$$

Where T is the board layer thickness, D1 is the pad width and D2 is the clearance hole.

In the article \$\epsilon_r\$is said to be the relative permeability. Is this a misprint? I thought that refers to the permittivity.

Doesn't permeability refer to the magnetic field? I would assume that the capacitance would be related to the electric field.

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    \$\begingroup\$ You should note that it is the capacitance of the via to a surrounding ground plane. The via itself alone could not have a capacitance. There is no capacitor with one terminal only. \$\endgroup\$
    – Uwe
    May 23, 2022 at 21:12
  • \$\begingroup\$ Ok got it. Thanks for the clarification. I did have some confusion about what a clearance hole is and how that compares with the diameter of the via. What's the difference? \$\endgroup\$
    – Aaron
    May 23, 2022 at 21:48
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    \$\begingroup\$ Look at figure 8 of the article, you see the diameter of the via and the diameter of the hole in the plane. (D2 - D1) / 2 is the width of the insulation gap between them. You need an insulation gap between two traces and you need an insulation gap between the hole in the plane and the via within the hole. \$\endgroup\$
    – Uwe
    May 23, 2022 at 21:57

2 Answers 2

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That is a typo on their part. The permittivity is what you want for the circuit board material. Which is about 4.3~4.7 for FR4.

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Yes, typo. They also use a ratio of cm^2/cm but don't cancel out the unit; presumably the "0.55" is supposed to have units of pF/cm, not just pF. So, including \$\epsilon_0\$ (units of ~F/m) as well as a geometric factor. (Assuming they're even using mks units at all; cm might suggest cgs, some variants of which omit many conversion constants..)

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