For this circuit, a PMOS input stage folded cascode amplifier as a gain booster, I have two questions. The PMOSs (Mppp1 to Mppp4) in the cascode banches are in strong-inversion saturation while the NMOSs (Mnnn1 to Mnnn4) are in weak inversion saturation (Vgs < Vth, but Vds > Vdssat). However, I don't manage to put the Mnnn1 to Mnnn4 in strong inversion saturation. Is this a huge problem when one side of the cascode is in weak inversion saturation and the other part in strong inversion saturation (Mppp1 to Mppp4)? The functionality seems fine to me. The figures are shown below.

A part of the schematic

Values of the weak-inversion saturation

The full schematic in LTspice file can be download from this link: https://drive.google.com/file/d/1Zr2CRn1vcVBtQ7_So4opipGoO-pey7_6/view?usp=sharing

Ideal CMFB: enter image description here

One more question, since the previous schematic is done with an ideal CMFB, the actual circuit should have a non-ideal CMFB. My implementation is seen below.

Important part of the schematic with non-ideal CMFB

Here, the Mppp9 and Mppp10 should be sized such that both the PMOSs are in deep triode. However, with this implementation in the tail part of the PMOS differential pair, the Mppp9 and Mppp10 are still in saturation whereas the Mppp6 is not in saturation. The other transistors are not in saturation, unfortunately. Hence, my question is: is it possible to implement the CMFB circuit in the tail part of the PMOS differential pair like what I did? Or is it better to use a different CMFB circuit before biasing?

Full schematic with non-ideal CMFB: https://drive.google.com/file/d/1x25jEk6ODmBD6e5xGWV-aiqN1jmcVJHP/view?usp=sharing

The model is given in this link for LTspice file: https://drive.google.com/file/d/1bwkuksGx4w6FvInAr4KF1ndcx49Y7NXU/view?usp=sharing

With kind regards, Kwok

  • \$\begingroup\$ Your link takes me to wetransfer signup page. Can you display the internal iideal CMFB here? Looks to me like your output devices are not saturated either. They should be when CMFB is settled or else (at the least) your gain benefits will suffer (output impedance drops). \$\endgroup\$
    – pat
    Commented May 25, 2022 at 18:40
  • \$\begingroup\$ @pat I have added it above and the links are now updated by using drive. Yeah it is true, since my non-ideal CMFB is just Mppp9 and Mppp10 in deep triode I dont manage to get the Mppp6 in saturation. But it is better to check my ltspice files, then probably you will understand what I mean. In the ideal case, I have tries to reduce the size of the transistors Mnnn1-Mnnn4, but I still dont get strong inversion saturation. Furthermore, VB2 in ideal CMFB is set to 0.39 to get Von_p = Vop_p = ~883 mV. \$\endgroup\$
    – Kwok
    Commented May 26, 2022 at 8:26
  • \$\begingroup\$ Ok. Can't run as you don't have model files. But, I wouldn't trust those vdsat numbers as vgs < vt. I would try to completely remove the CMFB and just work on bias and sizing to get the circuit balanced and devices saturated before you need any CMFB. \$\endgroup\$
    – pat
    Commented May 26, 2022 at 8:58
  • \$\begingroup\$ @pat thank you for your advice, I will try that first. But a differential folded cascode amplifier as gain requires a CMFB right? I have also attached the model file since I forgot to put it in the question. Maybe now you can open? \$\endgroup\$
    – Kwok
    Commented May 26, 2022 at 9:51

1 Answer 1


I have attached a simulation to show how you can approach tuning without using cmfb to design.

  1. You can just use ideal current sources to emulate the front end stage.
  2. You can tune the voltages and or w/l ratios to get the bias centered and devices in saturation.
  3. By designing this way you can add cmfb after (and reduce its range and workload). You need cmfb since a) it would be difficult to get exact bias voltages in production b) a slight change in process variation will likely push your output to the rails and kill the gain linearity.
  4. The table of operating point overdrive voltages are very small for the nmos devices (5-6mv). This could be a consequence of the process and or ltspice interpretation of the model files. The ID/VDS curves looked fine to me.
  5. you could have the cmfb control one of the output stage load devices instead. I think most analog designers don't use the one you have because it eats headroom.
  6. not sure if this is a school project or work, but generally analog designers do not use minimum length devices for current mirrors, output loads, and matching. Good job on the schematic and design from what I can see.

enter image description here

  • \$\begingroup\$ Thanks for your advice. This seems a good approach to start with biasing the cascode branches. Why do analog designers not use minimum lengths like 0.18 um? They use 2xLmin? \$\endgroup\$
    – Kwok
    Commented May 27, 2022 at 18:25
  • \$\begingroup\$ Mainly device matching (also it lowers output impedance, gain, etc). Usually 2-3X min. I learned that the hard way with real production design. Min length is good for speed and input and signal path devices but not high impedance and current mirrors. \$\endgroup\$
    – pat
    Commented May 28, 2022 at 18:24

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