Problem on biasing of the differential folded cascode with ideal and non-ideal CMFB

Question

For this circuit, a PMOS input stage folded cascode amplifier as a gain booster, I have two questions. The PMOSs (Mppp1 to Mppp4) in the cascode banches are in strong-inversion saturation while the NMOSs (Mnnn1 to Mnnn4) are in weak inversion saturation (Vgs < Vth, but Vds > Vdssat). However, I don't manage to put the Mnnn1 to Mnnn4 in strong inversion saturation. Is this a huge problem when one side of the cascode is in weak inversion saturation and the other part in strong inversion saturation (Mppp1 to Mppp4)? The functionality seems fine to me. The figures are shown below.

The full schematic in LTspice file can be download from this link: https://drive.google.com/file/d/1Zr2CRn1vcVBtQ7_So4opipGoO-pey7_6/view?usp=sharing

Ideal CMFB:

One more question, since the previous schematic is done with an ideal CMFB, the actual circuit should have a non-ideal CMFB. My implementation is seen below.

Here, the Mppp9 and Mppp10 should be sized such that both the PMOSs are in deep triode. However, with this implementation in the tail part of the PMOS differential pair, the Mppp9 and Mppp10 are still in saturation whereas the Mppp6 is not in saturation. The other transistors are not in saturation, unfortunately. Hence, my question is: is it possible to implement the CMFB circuit in the tail part of the PMOS differential pair like what I did? Or is it better to use a different CMFB circuit before biasing?

Full schematic with non-ideal CMFB: https://drive.google.com/file/d/1x25jEk6ODmBD6e5xGWV-aiqN1jmcVJHP/view?usp=sharing

The model is given in this link for LTspice file: https://drive.google.com/file/d/1bwkuksGx4w6FvInAr4KF1ndcx49Y7NXU/view?usp=sharing

With kind regards, Kwok

Answer 1

I have attached a simulation to show how you can approach tuning without using cmfb to design.

1. You can just use ideal current sources to emulate the front end stage.
2. You can tune the voltages and or w/l ratios to get the bias centered and devices in saturation.
3. By designing this way you can add cmfb after (and reduce its range and workload). You need cmfb since a) it would be difficult to get exact bias voltages in production b) a slight change in process variation will likely push your output to the rails and kill the gain linearity.
4. The table of operating point overdrive voltages are very small for the nmos devices (5-6mv). This could be a consequence of the process and or ltspice interpretation of the model files. The ID/VDS curves looked fine to me.
5. you could have the cmfb control one of the output stage load devices instead. I think most analog designers don't use the one you have because it eats headroom.
6. not sure if this is a school project or work, but generally analog designers do not use minimum length devices for current mirrors, output loads, and matching. Good job on the schematic and design from what I can see.