Is a full π-type EMI filter needed in front of an isolated DC-DC converter with long input cables?

Question

I want to use a 5-volt-to-5-volt isolated power via an isolation DC-DC converter, the Aimtec AM1/4S-0505SZ. This is a very small DC-DC with

• V_in: 4.5—5.5V
• V_out: 5.0V
• I_out: max 50mA
• f_SW: 80 kHz

Application information:

• Actual I_out needed: ~40mA
• Input cable length (to the DC/DC input): ~10 metres

Due to the need for long cabling, I think it's a very good idea to add an EMI suppression filter in front of the DC/DC, as suggested in its datasheet. However, this passage there puzzles me:

The first schematic shows an arrangement of an LC filter: inductor→capacitor→DC/DC. The second schematic shows a full π filter (capacitor→inductor→capacitor→DC/DC). However, for the 5V models, the table shows that C2 is to be omitted. I googled around and I saw that this is indeed the typical recommendation for other brands and models of DC-DCs (they all use capacitor→inductor→DC/DC), so I think the second schematic is more representative. Using the designators from the second schematic, I have the following three options:

Option	Name	C1	L1	C2	Comment
1	"Input Reflected Ripple Current Measurement"	None	12µH	47µF	Probably just optimizes ripple performance and not really recommended
2	Per datasheet table	2.2µF	18µH	None	Suggested in other datasheets, and maybe good enough?
3	Full π filter	2.2µF	18µH	47µF	Combination of both

Question

Is there any harm of placing both C1 and C2, as per option #3 above (2.2 and 47µF, respectively)?

Answer 1

Is there any harm of placing both C1 and C2, as per option #3 above (2.2 and 47µF, respectively)?

It's a risk doing something that the data sheet doesn't recommend.

For instance, with the series inductor and C2 (not specified by the data sheet), if the input supply was energized fairly quickly, the inductor and C2 can produce an output waveform of a decaying sinewave whose peak voltage might be close to double the incoming 5 volts to 10 volts. That would exceed the maximum input voltage rating for the device (7 volts) and, potentially destroy it.

So, you might ask, why can they get away with C2 for converters that are 24 volt nominal input? The devil will be in the detail (if indeed the manufacturer have properly looked into this). The 24 volt rated devices have more input stage losses (as can be seen on page 1 with the no-load input current). For 24 volts it's maybe 8.5 mA whereas, for the 5 volt version, it's about 17 mA.

In other words, the 24 volt device consumes about 204 mW no-load whereas the 5 volt device consumes about 85 mW no-load; meaning that the 5 volt device presents less of a loss to the tuned circuit formed by L1 and C2 and, this might just be enough to cause the input voltage at the terminals of the converter to exceed 7 volts when the input supply is switched on fast.

So, it's not only a risk doing something that is not recommended on the data sheet but, it's an added risk when you can fathom out a mechanism that might justify the words in the data sheet.

Of course, this is just speculation on my part but, I wouldn't fit the C2 capacitor. If I felt that the C2 capacitor did bring something useful to the party, I would place a 6.2 volt Zener diode (or TVS) in parallel with it to limit the peak voltage to less than 7 volts.

Due to the need for long cabling...

It's a no-brainer for me; fit a Zener or TVS diode (both of which will protect you against reverse voltages too).

Answer 2

In addition to Andy's answer, in general, if you place an inductor between two identical caps, this will tend to severely exacerbate the resonance between them.

For an 18µH inductor between two 2.2µF capacitors, it will tend to be highly self-resonant at ~25kHz. This can be illustrated if we briefly "pulse" such a network and see how it responds:

Notice that some of these peaks are above 5.5V. This is why a Zener is a good idea.

If however C2 is changed to 47µF, then these are not well-matched, so resonance is reduced and the frequency lowered to about ~5.4kHz:

Notice that the peak oscillation is a much lower amplitude, due to the differing capacitances. But still, it does oscillate some, which could manifest as a reduction in filtering (even slight oscillation) at ~5.4kHz.

Sadly, LC filters create just about as much trouble as they remedy. I'd suggest in your case with the long cable, to create the design with pads for these components and test it. Use an oscilloscope with 100x probe and short spring ground for highest bandwidth. Observe the behavior at the regulator input both with and without C2/Zener. It may be, that the inductance of the long cable is sufficient without C2. Or C2 may help significantly (or it may help but exacerbate noise at 5.4kHz.)

Answer 3

Follow the data sheet. There could be several reasons why C2 is not required for the low-voltage devices. One is that they operate at higher switching frequencies than the higher voltage parts, and a 2.2µF might be above its own resonance frequency, so making emissions worse instead of better.

Answer 4

Without knowing the s22 or Zout(f) of the 5V source and the s11 or Zin(f) of the converter, you can only guess what resonances will happen and interact between two SMPS.

Generally, you test this with pulse load tests or impedance plots then design a filter, not guess and cross your fingers.

With load-regulated noise on the right sweep and output to 5V source on the left the 1st cap on the right does nothing from true AC voltage source or large-cap.

Here might attenuate input egress 50 dB better at 80 kHz switching rate back to the source but make it's DCDC load regulation worse with a higher source impedance.

I might expect a common mode choke and differential lossy ferrite beads for EMI reduction of 80 kHz input noise and a low impedance differential twisted pairs or traces in between. (maybe a possible solution or one of the datasheet examples.)

It all depends on s22, s11, and s33 as it is the impedance ratios of these functions that determine attenuation or resonance gain then s21 for forward transfer function and phase margin plots.