Consider HDL code below:
module top_module ();
reg [2:0] a, b, c;
initial begin
a = 3'b001; b = 3'b010; c = 3'b011;
end
initial begin
#5 $display ("a = %d, b = %d, c = %d", a, b, c);
end
initial begin
a <= b;
b <= c;
// b <= a;
$display ("a = %d, b = %d, c = %d", a, b, c);
#50 $finish; // Quit the simulation
end
endmodule
The output is:
Running Icarus Verilog simulator...
a = 1, b = 2, c = 3
VCD info: dumping is suppressed.
a = 2, b = 3, c = 3
Hint: Total mismatched samples is 0 out of 0 samples
Simulation finished at 50 ps
Mismatches: 0 in 0 samples
In the above code: (a = 1, b = 2, c = 3) initially: Scene-1:
a <= b;
b <= c;
I get: a = 2, b = 3, c = 3; Hence initial, un-updated value of b. (a = 1, b = 2, c = 3) initially:
Scene-2:
a <= b;
b <= c;
a <= c;
I get: a = 3, b = 3, c = 3;
Even more, if I do this:
Scene-3:
a <= b;
b <= c;
a <= b;
then too I get: a = 2, b = 3, c = 3;
In scene-1 and 3, a is getting the value as per the older assignment of b, but in scene-2, it is getting the latest value as per the latest assignment of c. I'm trying to wrap my head around this, need to get better understanding of this.
a <= b;
, you're not changinga
, you're saying "the next value of a will be the current value of b". If then you writea <= c;
, it's like you've changed your mind and would rather have the next value of a be the current value of c instead. Only when the next tick happens (in your scenario) do the values actually change - and they take up whatever the last assignment you wrote say they should. \$\endgroup\$