I'm an electronic engineering undergrad and your discussions helped me a lot. As a project, i was instructed to design the front end for a data acquisition system. The specs as below.

  • Supply +/- 5V DC
  • AD 8065 (This was specifically given)
  • Two attenuation modes 1/10 and 1/100 (I properly tuned and tested it)
  • Input impedance is 1 MOhm and 15 pF (Same as an oscilloscope)
  • Amplifier gain is 2 non-inverting

So, I built the example circuit given in the datasheet and connected it to the attenuator. The problem is i'm getting a huge offset around 200mV when the attenuator input is zero. It is also changing when i change between two attenuations. But the offset indicated in the datasheet is around 1-2 mV. I tried simulation with LTspice but it didn't indicate any offset like this.

After playing around a bit (I just connected a pot to the inverting input and turned it until the offset is zero) , I've found a solution as this.

For the 1/10 attenuation

enter image description here

For the 1/100 attenuation

enter image description here

After adding the resistor, the offset is almost zero volts but i think this is not a standard topology. To be sure, i have tested the circuit with 2 ICs but the results are same. I also tried adding a series resistor to the non inverting input but it is increasing the offset.

I ordered the chips from the Aliexpress so i'm not sure about their authenticity. Can anyone help me with this? I just want to decrease the offset without affecting the amplifier operation. I'm not sure where the problem is.

Thank you!

  • \$\begingroup\$ Post a picture of the parts (so the markings can be closely examined) and add the link for where you bought them please. Quite possibly they are fakes. Aliexpress is notorious for this IMHO. \$\endgroup\$
    – Andy aka
    May 28, 2022 at 16:07
  • \$\begingroup\$ The chips are SOT-23 packaging marked as "HRA" (Now i'm away from home.. i will post a pic asap) the link is a.aliexpress.com/_mqyat1u \$\endgroup\$
    – HasithaCG
    May 28, 2022 at 16:20

2 Answers 2


Unbalanced Input resistors with common mode input current creates an additional input offset voltage.

Thevenin equivalent resistance into Vin+,Vin- with input bias current at 25'C

Total input offset = Vio + Iin(Req+ - Req-) with tolerances and tempco on all values.

CMOS or FET input Op Amps are made with very low input Iin to support a wide range of resistance offsets.

Since these are FET input Op-Amps and the offset reduced with resistor balancing, that tells me the input bias current was much higher than the spec in the datasheet.

That means they are off-spec either by supplier rejects or ESD damage and diode leakage from mishandling.


In your two different attenuation modes, you have effectively two very different impedances from the op-amp non-inverting input to ground. 10k || 990k = 9.9k vs. 100k || 900k = 99k --- or a change by a factor of 10.

By having two different impedances to ground on the non-inverting input, it becomes problematic setting the impedance to ground on the inverting input in such a way that you get zero offset voltage in both modes.

An alternative switchable attenuator has significantly less variation in the impedance to ground seen by the output.


simulate this circuit – Schematic created using CircuitLab

When SW1 is set to the 10:1 position, the effective impedance to ground seen by Vout (i.e. the op-amp's non-inverting input) is 900k || (90k + 10k) = 90k. When SW1 is set to the 100:1 position, the effective impedance becomes 80.1k + (10k || (90k + 900k)) = 90k. So, you have the same impedance to ground at the non-inverting input whichever attenuation setting you use. This should make the op-amp bias current the same for both settings, and hence the offset voltage the same for both settings.

This, however, does not reduce the offset to zero, but merely makes the offset equal for both attenuation settings. To make the offset close to zero, one wants the bias current at the non-inverting and inverting pins to be equal. To do this, the impedance to ground seen at both input pins must be the same.

We cannot conveniently reduce the impedance to ground seen by the non-inverting input pin without simultaneously increasing the attenuation of the input resistor network. (While keeping the overall input impedance at 1 M\$\Omega\$). However, we can reduce the impedance to ground seen by the non-inverting input pin if we simultaneously increase the closed loop gain of the op-amp. (510 \$\Omega\$ is kind of low for feedback network resistors in this situation anyway).

  • 1
    \$\begingroup\$ 80.1k isn't a standard resistance value, but 80.6k (which is in E96 and E192) is probably close enough. \$\endgroup\$
    – Hearth
    May 28, 2022 at 20:20

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.