Slew rate of two stage OTA

Question

I have learnt two stage opamp designing from books and yourtube videos, but have always failed to understand slew rate formula which is I5/Cc(I5 is bias current of M5 and Cc is compensation capacitor). Always thought that slew rate should depend on load capacitor and not compensation capacitor. After thinking a lot I finally simulated by giving opposite phase square wave to input and looked at all current values. It looks like the load capacitor is getting charged by second stage PMOS and discharged by second stage NMOS. It seems like the contribution of current from first stage is very small. If this is true shouldn't the slew rate be a function of current of second stage transistors and load capacitor?

I have attached one image for your reference, the up arrow means voltage is going from zero to vcc and the down arrow means voltage is going vcc to zero.

Answer 1

If this is true shouldn't the slew rate be a function of current of second stage transistors and load capacitor? Yes.

In a two stage miller compensated op amp, slew rate is a function of input bias current and compensation capacitance and is often used to design the operational amplifier in texts.

However, you should be able to see that if the load capacitance is dramatically increased beyond the internal compensating capacitance, then the ability to maintain the same slew rate (measured at the output under an external load capacitance) requires either larger current in the input stage or larger current in the output stage. There has to be enough total current to drive a total max load capacitance and maintain a targeted slew rate.

"Normally, slew rate is not limited by the output, but by the current sourcing/sinking capability of the first stage." Allen, Holberg. Analog Ciruit Design 2nd edition.2002

"The overall slew rate is either limited by the first stage or the second stage, whichever is slower. The proper bias current can be determined by SPICE simulation" Silveria, VLSI systems on a chip, 1999

Answer 2

For a rising output, the current is supplied by M6. If the output slew rate is low enough) such that M6 can easily supply the current CL.dV/dt, then the slew rate will be dominated by Cc at I5/Cc (basically this presumes that the voltage changes at the gate of M6 are negligible compared to the drain changes; this is equivalent to considering that M6 can "easily" supply the required current).

For a falling output, M6 may turn off, and only M7 can sink the required current. Likely M7's current is lower than that which M6 could supply, so the slew rate down is limited by M7's (DC) current. At output slews slower than this, Cc will still dominate the actual slew rate (this means that M6 is still supplying some current.

Answer 3

For the output to ramp up or down, current has to flow through Cc, because M6 gate voltage is approximately constant. This current has to be sourced or sunk from the right input leg.

The maximum charging rate in both direction is Id of M5, which you can visualize by either turning M1 or M2 off. Either it is directly sunk through M2 and M5 or it is sourced from M4 after being mirrored.

Answer 4

In slew condition, M6 gate voltage is not constant; the amp is no longer linear. The comment that "slew rate is limited by the input stage bias current" is only true if the output stage bias is significantly larger (3-5x) than the input stage bias. This was true in the olden days, when the output stage had to drive real-world (board-level) loads. When driving on-chip, given noise/distortion requirements it's quite possible that the input stage bias is higher than output.

Think of it this way - whenever the comp cap is charging/discharging, the same current has to flow into both terminals by charge conservation. The only current available on the M6 gate side (high-z) is the input bias, the only current available on the M6 drain side (Vout) is the output bias. Whichever one is largest is the maximum available current for slewing Cc.

As a quick example, consider if Vout is trying to drive downwards as fast as possible. Then the current available in M7 is going to two places - output cap load and Cc. ZERO current is available to keeping M6 alive, and so to sustain this maximum voltage transient M6 Vgs has to go below threshold. So the gate potential on M6 goes up (trying to shut down the M6 PMOS). The only current on the other side of Cc is the current in M4, which is effectively the input bias of M5 being mirrored around. So maximum slew rate across Cc is set by max(abs(M7 current, M5 current)).

Slew behaviour can get super complex, since you're dealing with a whole mess of capacitors charging/discharging. One cap that can really mess you up is the gate cap on M6 - if the output stage is large, Cgs on M6 can be comparable to Cc (and if you try to scale the Cc to dominate, the parasitic on Cc adds into that node as well). Yes, Miller effect is in-play here, but Miller only helps if M6 is not cut off (which is why slew behaviour can be really weird and asymmetric between pullup and pulldown).