I want to simulate how a computer works using logic gates. Right now I am trying to build the memory aspect of it.

After looking at various articles and books I see a lot of them using flip-flops/latches to build the memory and I was confused about how they arrived at the circuit diagram because I was used to deriving logic circuit diagrams from truth tables.

After doing some research, I have seen the two inverted gates and a feedback loop.

enter image description here

The And Or latch

enter image description here

Most times always settles back to the criss-cross flip flop.

This is what I mean when I ask why they are criss-crossed:

enter image description here

I haven't gotten a satisfactory knowledge of storing a one-bit data, this is why this is used, this why this is like this and so forth.

I know most of the intricacies will be on electronics, but I just to understand it.

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    \$\begingroup\$ What do you mean by "criss-cross"? The way a SR latch implemented with NAND or NOR gates is usually drawn? \$\endgroup\$ Commented May 30, 2022 at 8:30
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    \$\begingroup\$ They criss-cross because we normally draw the gates with the inputs on the left and the outputs on the right. If you flip one of the gates around or place them one after the other, the criss-cross is eliminated, and the positive feedback loop becomes more obvious. \$\endgroup\$
    – Dave Tweed
    Commented May 30, 2022 at 9:40
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    \$\begingroup\$ Several reasons probably. A flip flop is a very basic logic element and well described in lots of books and web sites. And you've asked additional questions that could also be answered by some basic research. \$\endgroup\$
    – Finbarr
    Commented May 30, 2022 at 10:32
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    \$\begingroup\$ How flip-flops can be drawn in various different ways does not depend on what it does or how it works so those two concepts are not related and should be kept separate. And of course flip-flops are not the only way of storing bits, as there are various different types of memories. For example, bits have been stored as sound waves in mercury vapour in the early days of computing. \$\endgroup\$
    – Justme
    Commented May 30, 2022 at 21:10
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    \$\begingroup\$ @Justme Not Hg vapor- liquid mercury delay lines, also see this patent. Before my time. \$\endgroup\$ Commented Jun 2, 2022 at 16:34

6 Answers 6


The criss-cross layout is simply a compact way of drawing the two inter-connected gates.

Since that drawing layout is compact and convenient, it has become a "standard" and easily recognized way to draw a flip-flop.

A further thought: the criss-cross arrangement implies to me that the two gates work together, while the horizontal arrangement in your second drawing implies the left gate does something, then feeds the result to the right gate - it doesn't "look like" the two gates work together.

  • \$\begingroup\$ the And or Or latch is defined as a form of flip flop. Does that mean that I can’t be used to store state if the gates are not working together? \$\endgroup\$ Commented Jun 15, 2022 at 20:30

The circuits are exactly the same. criss-crossed


All three circuits you've drawn are identical.



simulate this circuit – Schematic created using CircuitLab

  1. -> 2. Add two inverters in series to output of A1: those don't change anything.

  2. -> 3. Merge A2 and D2 into a NOR AD3.

  3. -> 4. Apply DeMorgan's identity to inverted inputs AND C3.

  4. -> 7. Just rearrange things visually.



simulate this circuit

  1. -> 9. We want an "idle" SR latch that just keeps its state. The S and R inputs are fixed to 0.

  2. -> 10. An OR gate with one input set to zero is just a BUFFER gate. A NOR gate with one input zero is just a NOT gate.

  3. -> 12. Rearrange things visually only.

The way I personally "derive" all latches is by starting with static circuits with feedback: just a bunch of buffers or inverters in line, with closed feedback. The buffers and inverters can be converted to AND/NAND respectively with the 2nd input set to "1", or OR/NOR respectively with the 2nd input set to "0". Then you can explore what functions those extra inputs have.

Can a F/F be implemented with AND/OR gates only?



simulate this circuit

It just happens that the RESET input has inverse (negative) logic. And it doesn't have a complementary output (~Q), just two Q outputs. That's all.



simulate this circuit

  • \$\begingroup\$ Thank you so much for this answer @Kuba hasn’t forgotten Monica, I have a question. 1) does that mean that the complementary output( Q = notQ) is not important, but preferred for uniformity across design maybe. That’s why the nand/nor gate is mostly used. \$\endgroup\$ Commented Jun 16, 2022 at 6:00
  • \$\begingroup\$ @UkpaUchechi Well, it’s all besides the point, as real flip flops aren’t usually built out of gates, but out of transistor structures that work better than gates would. In other words: no gates are mostly used. The gate thing exists solely in textbooks and in simple circuits where someone had extra gates and needed a flip flop. These days a FF costs more to talk about than to put into a product whether it’s a discrete SOT part or in an PLD/FPGA or an ASIC. \$\endgroup\$ Commented Jul 4, 2022 at 22:10

Elementary computer building blocks, like any circuits, were invented not so much in a logical way but rather through intuition, imagination and common sense. Then, they are used to build more complex logic circuits through formal methods. In essence, they are analog circuits that are forced to work as digital. So, normally they are digital but during the transition they act as analog.

There are many ways to store data. Most of them use all sorts of physical effects but here a "circuit way" of memorizing based on the principle of positive feedback is used. To understand how, let's look at a possible scenario for inventing this memory circuit.

Building scenario

1. A non-inverting amplifier without memory. Logic gates are amplifiers... but amplifiers have no memory. For example, if we apply a voltage to the input of a non-inverting amplifier, a higher voltage with the same polarity will appear at the output. When we remove the input voltage, the output voltage will dissapear. How can we make it stay that way? How do we make the "forgetting" amplifier remember?

Non-inverting amplifier_250

2. A non-inverting amplifier with memory. The recipe is very simple - just connect its output to its input. Thus, the amplifier will produce its own input signal. The name of this trick is "positive feedback".

Non-inverting amplifier with positive feedback_250

3. Cascaded inverting stages. But in general, transistor amplifier stages are inverting. To make them non-inverting, we connect one after the other (cascade) two inverting stages. Indeed, there is another reason to do so, and that is to be able to toggle the circuit by two separate inputs.

Cascaded inverting amplifiers_500

4. Symmetrically drawn circuit. If we move one element over the other, we will get a beautiful symmetrically drawn circuit...

SRAM cell_250

5. ... that can be simultaneously controlled on both sides (left and right). This drawing is used in SRAM structures where this circuit acts as an elementary memory cell. Note that there are no additional inputs (the low-power circuit is "forcibly" controlled by many times more powerful bit lines). This greatly simplifies the organization of memory.

SRAM cell controlled_500

6. Cross-coupled pair. When using this circuit as a latch (flip-flop), we add additional inputs to toggle it "gently". We prefer to draw the inputs on the left and the outputs on the right. For this purpose, we "twist" the circuit as the number "8" and name it cross-coupled pair (or, if you prefer, "criss-crossed").


So the answer to why this circuit is cross-coupled is simply, The circuit is cross-coupled because it is drawn cross-coupled.

Transistor version

If you really want to understand this circuit, I recommend you watch my movie in which I build a latch with real transistors. These are two cascaded amplifier stages "common emitter" visualized with LEDs.


This "circuit way" of memorizing allows to read/write data at high speed. Another advantage is that the memory cell is implemented by conventional elements (logic gates).

EDIT: Is it possible to implement flip-flops with AND or OR gates?

you mentioned that they have to be inverters, what of the case of the And or Or latch that is not inverted

Your question is very relevant... and I had to think a little to find an answer...

In my opinion, the main reason that a flip-flop cannot be done with (two) non-inverting logic gates AND and OR is that it will not be able to change its state (the logic gates will be uncontrolled). Let's see it in a latch made by one AND...

1-AND latch

... and made by two cascaded AND.

2-AND latch

When it is implemented with inverting logic gates, for example NAND, they alternate - through one logic gate we can set it in "1" (by applying "0" to its second input) and it loses its control properties; then we can set it to "0" through the other logic gate (again, by applying "0" to its second input)... and again, it loses its control properties.

See also my answer to a related question illustrated by CircuitLab simulations.

  • \$\begingroup\$ Thank you for your response, please I have to ask, for the positive feedback diagram if the circuit is off won’t the current still be lost regardless. Also for the two inverters can a buffer be used instead? \$\endgroup\$ Commented Jun 8, 2022 at 11:01
  • \$\begingroup\$ @Ukpa Uchechi, I guess your question is whether after turning off the power the circuit will return to its old state? If so, here is my answer: It usually returns to the same state it prefers; ie, stored data is lost. This is the big disadvantage of RAM (as they say, it is a "volatile memory"). \$\endgroup\$ Commented Jun 8, 2022 at 12:32
  • \$\begingroup\$ @Ukpa Uchechi, The two inverters can be anything as long as it amplifies (K > 1) and inverts. As you can see in the movie above, I have used the simplest "common emitter" transistor amplifier stage. In flip-flops, we prefer to use inverting logic gates (NAND or NOR) with two inputs since the one input is used by the positive feedback and the other by the input signals; so there is not a conflict between voltages. \$\endgroup\$ Commented Jun 8, 2022 at 12:41
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    \$\begingroup\$ Thank you @Circuit fantasist for your answer, please I have a few questions 1) flip flops are bistable multivibrators which I understand is, that a single output can either be in an on-state(1) or off-state (0). is this correct? 2) I am thinking that when the state needs to change, it kind of flips the state of the two outputs that's why the outputs have to be in the inverse of each other. 3) you mentioned that they have to be inverters, what of the case of the And or Or latch that is not inverted \$\endgroup\$ Commented Jun 15, 2022 at 17:42
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    \$\begingroup\$ I hope my questions are clear and make sense \$\endgroup\$ Commented Jun 15, 2022 at 17:43

You can't analyse sequential logic (latch/flipflop) with truth table as it depend on logic state before. What you need to know is, without any input, the output stay the same. When set input is high, output become high and vice versa. As you says you want to simulate the computer system with logic gate. For memory part you should consider at as functional block. It too complicate to simulate flipflop with logic gate.


Just for completeness, here is an example of a D flip-flop that does not require an inverting logic function and does not rely on hysteresis.


simulate this circuit – Schematic created using CircuitLab

When CLK is high, the left latch is in the HOLD state...the feedback through MUX1 forms a positive feedback path that holds the current state. At the same time, the right latch is transparent, meaning that the value at the 1 input of MUX2 simply propagates out to the Q output.

When CLK is low the left latch is transparent but the right latch is in the hold state.

This is the classic behavior of the so-called "master-slave" flip-flop.

Now it is true that a CMOS implementation of a buffer will be constructed from two inverters, but the point here is that the flip-flop itself does not depend on an inverting logic function. The multiplexers are formed from two CMOS transmission gates, again a non-inverting function. Likewise, the circuit does not depend on hysteresis. The one characteristic that is critical is propagation delay...the delay through each latch must be greater than the transition time of the clock.

  • \$\begingroup\$ Just for completeness, there is an inverting logic gate inside the multiplexer:-) \$\endgroup\$ Commented Jul 2, 2022 at 15:50
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    \$\begingroup\$ @Circuit Not necessarily. The inversion of CLK can be done globally rather than inside the mux. Or the MUX could be made with one NMOS transistor (the '1' path) and one PMOS transistor (the '0' path). The point is that the function of the flip-flop does not require an inverting logic gate. \$\endgroup\$ Commented Jul 2, 2022 at 16:49
  • \$\begingroup\$ Of course muxes can use both P-element and N-element pass gates, so no inverters needed. \$\endgroup\$ Commented Jul 4, 2022 at 22:13

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