Potential distribution in MOSFET

Question

Let us assume that an NMOSFET has its source, drain and substrate grounded therefore V_DS and V_SB=0 V . We apply a gate voltage V_GS=2 V and I want to know how this potential is distributed as we move from gate towards substrate.

Let us assume the threshold voltage to be V_T=0.7 V. Now I know that since the MOSFET is in inversion, a charge density Q_inv= C_ox*(V_GS - V_T) will appear in the inversion layer. The threshold voltage will be divided into two parts:

1. Change in surface potential from φ_S to -2φ_f where φ_f is the bulk fermi potential.
2. To support the depletion region charge due to increased depletion region width at inversion.

Let us assume that V_T is equally divided between these two components and assign 0.35 V to both. Now I believe that potential at the surface under the gate must be atleast at 0.35 V because we still need to account for bending of band and change of surface potential but since the MOSFET is under inversion, an inversion layer links the surface, drain and source and therefore they must be at 0 V (since we assumed they are grounded). So where am I going wrong?

Edit: https://demonstrations.wolfram.com/AppliedVoltageOnAnIdealMOSCapacitor/

This demonstration simulates the effect of an external bias on a MOS capacitor. I checked the graph of electrostatic potential as I increased the gate voltage and I found that V_Surface increases indicating that some part of applied voltage is used to increase the surface potential to cause inversion. There is a potential difference between surface and substrate. But since in MOSFET we have grounded source, drain and substrate to 0 V and source, drain and surface are connected through an inversion layer in inversion mode, we have set V_Surface to be at 0 V. So there is no potential difference between surface and substrate. Then how can we achieve inversion?

Answer 1

The potential throughout the channel will be the same as S and D (i.e. 0).

This is because that is a continuous conduction region with no current flowing.

The potential across the GOX will be VG.

There is a slight twist to this - if you define '0V' as the V at the external S terminal, then due to work function difference, the actual V will be non zero, but this is not observable.

An excellent book on this is 'Operation and Modeling of the MOS Transistor' by Tsvidis and McAndrew

Answer 2

Potential through the drain and source will be zero.

Answer 3

My understanding is that most of the surface potential is dropped across the oxide portion under the gate, with D/S/B tied to ground. This seems consistent with your comments.

Sources.

1. "In inversion and accumulation , the vast majority of the gate voltage is dropped across the oxide

In inversion, the depletion width remains ~ constant Thus, φS can not be much less (greater) than 0 for p-type (n-type)

Thus, φS can not be much greater (less) than 2φF for p-type (n-type)"

2)"We take N-channel MOSFET as an example to analyze the capacitance with the source/drain connected to the bottom (substrate). The capacitor composition between the gate and bottom is shown in Fig. 1(b), where the red line is electrically connected.

If the gate voltage is smaller than a threshold voltage Vth, the total capacitor still performs like a MOS CAP because an inversion layer is not yet formed to short-circuit the depletion region. However, when the bias voltage becomes larger than Vth, the formed inversion layer, source, drain, and bottom are connected as one terminal to shortcircuit all the capacitors among them. After that, only the oxide capacitance is left since one of its terminals is the gate. The total capacitor between the gate and bottom quickly increases from Cdep to Cox, which is the total oxide capacitor. The deviation is usually more significant than 50% as shown in Fig. 1(c), because Cox is larger than Cdep."

Answer 4

The above explanation is very clear in terms of vertical potential. One quick note when you go from source to drain just under the oxide (channel of Silicon), is the VDS is mainly drops across depletion region of pinch-of or depletion region between drain and body or depletion region between source and body. They actually act as a capacitor, C_body/drain and C_body/source. So, I think if you think it that way, you would be able to see the channel under the oxide with phi_s coming from VG.