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I still don't seem to understand the basics of MOSFETs, I was looking over this slide from a lecture but I don't understand how the gain was solved for.

PMOS CS Stage with NMOS as Load

Can someone explain to me how the gain was found?

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  • \$\begingroup\$ Similarly to the previous slide? \$\endgroup\$
    – user16324
    Commented Mar 25, 2013 at 9:50
  • \$\begingroup\$ i50.tinypic.com/iy094w.png Yeah, I get the analysis after getting a circuit into that sort of form... I don't understand how/what to replace the FET with though. \$\endgroup\$ Commented Mar 25, 2013 at 16:12

1 Answer 1

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You have to replace the FET with its small-signal model. When the devices are in saturation (as they should be in a CS amplifier), the equation that describes the drain current of a FET with respect to its gate source voltage is

$$ I_{D} = \beta \frac{W}{L}(V_{gs}-V_{T})^2 $$

where \$\beta\$ is the FET's transconductance (a parameter calculated from the mobility of its carriers and the oxide capacitance) \$V_{gs}\$ is the FET's gate source voltage and \$V_{T}\$ is its threshold voltage. That equation is non-linear and hard to solve, so for "small" AC signals we choose a "large signal" DC operating point and linearise the equation at that point by differentiating it with respect to \$V_{gs}\$ to give the small signal transconductance \$g_{m}\$. Similarly, the FET's channel resistance can be found by differentiating \$V_{ds}\$ with respect to \$I_{D}\$. That allows you to derive the small signal model below.

schematic

simulate this circuit – Schematic created using CircuitLab

Replace the FETs in the slide with that, and you can analyse the circuit (note that a lot of second order effects like channel length modulation, body effect etc. are left out of this explanation).

The lower FET has both its gate and source at AC ground, so the complete small signal model is as below, and you can see how the gain is derived.

schematic

simulate this circuit

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