Working on an application which may require to change the FPGA (Xilinx) clock frequency dynamically at runtime (between two different clock frequencies) so wanted to ask is it at all possible to do so if the clock is being provided by an external clock source and if so then what should be done additionally (to ensure smooth functionality and accurate working)?

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    \$\begingroup\$ It is likely, that most things should run normal with a slower-than-max clock. Read about glitch-free clock switching, to avoid one or two dangerously short clock cycles as you switch. \$\endgroup\$
    – tobalt
    Jun 1 at 17:06
  • \$\begingroup\$ @tobalt Thanks for your response. So apart from handling the transient clock cycles there should be no issue or additional requirements to make it run smoothly as long as timing requirement of the max clock is met? \$\endgroup\$
    – malik12
    Jun 1 at 17:50
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    \$\begingroup\$ Do you need to change clocks or change clock frequencies? If it’s just frequencies, you can pass your external clock signal through one of the PLLs and modify the frequency dynamically. Read the FPGA documentation for details. \$\endgroup\$
    – user110971
    Jun 1 at 17:59
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    \$\begingroup\$ The MMCM/PLL should be reset if the input clock is changed. Monitor the LOCKED output - if it goes unlocked (which it will if you change input clock) then you must issue a reset for a few clock periods after the new clock is selected. \$\endgroup\$
    – td127
    Jun 1 at 21:52
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    \$\begingroup\$ @td127 Right thank you. I think this is what I was looking for. If you can post this in the answer I'll mark it to close the question if no one else has any other input in this regard. \$\endgroup\$
    – malik12
    Jun 2 at 12:40

1 Answer 1


From Xilinx app note UG382, the DCM/PLL must be reset to re-lock to a new clock input. Reset should remain asserted for a minimum of three of the new clock periods.

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