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VERY SPECIFIC QUESTION, PLEASE READ THROUGH ALL OF IT

From wikipedia:

"The sequence of operations that the control unit goes through to process an instruction is in itself like a short computer program, and indeed, in some more complex CPU designs, there is another yet smaller computer called a microsequencer, which runs a microcode program that causes all of these events to happen."

My question is: Before the microsequencer and the microcode, how did they make CPUs to physically step from one point of the sequence to another? What was going on in those CPU designs BEFORE the "more complex" ones we have today? If that "sequence of operations the control unit goes through to process an instruction is in itself a short computer program", like Wikipedia claims, then who's executing it? Answering "The CPU itself" won't help cause the CPU executes user-defined programs exploiting the fetch-execute cycle, so it can't execute the fetch-execute cycle itself too, right? I mean, this piece of hardware responsible for creating the fetch-execute cycle should still be located somewhere inside the CPU, but it's not what people refer to when they say "the CPU". It's at a lower level of abstraction, it's what's given for granted in EVERY, EVERY, EVERY resource about CPU's internal functioning (at least the non-academical ones) that I've found so far. I can't find this information anywhere.

Please don't answer "The program counter points to the memory address to fetch the next instruction from". I know that, I just don't know how this sequentiality is actually/electrically/physically implemented. I would need a more straight up electrical answer. I know what a finite state machine is and I know that at its core the CPU is one. But that still doesn't answer "how is a FSM realized in a CPU without a microsequencer?". The microsequencer should still rely on this "sequential automation device" (the thing I'm asking about) to work.

My only mental approximation of how such automated sequenciality could work is only mechanical, not electrical (it's the piano player), and I know there are no moving parts on a computer. The Jacquard loom isn't a good example here either because it was not automated, the weaver would have to manually pull the wire that made the metal drum rotate so that the machine could read the set of punched holes in the next card. I'm also not asking anything about the clock pulse nor synchronisation.

Notice that this isn't even a very technical question and as such shouldn't require a too technical answer too, as those I was given earlier. Literally, in the most intuitive sense, when you read "this machine is automatic" you wonder by which means it's automated. The same I'm asking in regards of computers. If you say "the CPU automatically steps through a sequence of always-the-same processes, a loop", I'll be tempted to ask you "How is this loop realised?". This should be a technology invented somewhere in the 50s, because that's about the time people stopped manually plugging/unplugging wires into those room-sized mainframes just to tell the machine to add stuff. As such an old technology, it suggests me it shouldn't be that complicated to understand even for me as a chemistry student. But it also should have been a very revolutionary discover, so it baffles me how I wasn't able to find it anywhere. Is it really that complicated that it's only talked about between engineers?

Thank you very much for reading!

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    \$\begingroup\$ I highly suggest Ben Eater's "Build an 8-bit computer from scratch" series (eater.net/8bit - youtube playlist youtube.com/playlist?list=PLowKtXNTBypGqImE405J2565dvjafglHU) \$\endgroup\$
    – Mat
    Commented Jun 2, 2022 at 18:22
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    \$\begingroup\$ You're asking us to summarize something that takes two semesters of undergrad classes and hundreds of pages of textbook space in a few paragraphs. You have unrealistic expectations of how much understanding you will be able to obtain from a few paragraphs of text. If you want a more complete answer, get a textbook and read it. \$\endgroup\$ Commented Jun 2, 2022 at 18:24
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    \$\begingroup\$ I think you are trying to skip several stages. I do not know what your goal is, but the usual path to reach some understanding on the topic would be "Boolean logic" -> "combinatorial circuits" -> "sequential circuits" -> "final state machines". From there you have a certain background to understand a simple CPU architecture. This all is usually covered by "digital design" textbooks and courses. And even though it might sound a bit scary, this is the easiest and most enjoyable subject in EE study (maybe subjectively) \$\endgroup\$
    – Eugene Sh.
    Commented Jun 2, 2022 at 18:25
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    \$\begingroup\$ See if you can make a 16-bit counter from the 4-bit counters in the TTL Data Book. Then address a memory using that counter, and read a byte from it. Then, if that byte = C3, load 2 more bytes from the next 2 addresses in memory (saving the first in a register) and having accessed the second byte, load the counter from them both. Congratulations, that was the Intel 8080/Zilog Z80 "Jump" instruction. \$\endgroup\$
    – user16324
    Commented Jun 2, 2022 at 18:51
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    \$\begingroup\$ Do a search for EDUC-8. This was a 70's project in an Australian electronics magazine. There's no microcoding involved in the control unit. The data path is also bit serial for some extra fun. The design and operation is extensively described. The complexity is at a level where you can use pen and paper to work out the logic without too much effort. Get that under your belt and see where it takes you. \$\endgroup\$
    – Kartman
    Commented Jun 2, 2022 at 22:39

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Several have commented on the use of finite state machines. At the heart of a finite state machine is a register. Its contents—a number—identify the current state of the machine. The processor designer adds logic around this register. This logic considers the current state (and possibly inputs) and then creates outputs based on all the data it is considering. Among the outputs is the next state to be loaded into the state register. Other outputs are used to control such devices as an arithmetic logic unit, a memory device, and so on. The whole process is synchronized by the leading edge of the clock. When the clock strikes, the desired next state is loaded into the state register, and the cycle repeats, generally with different results since both computer instruction and data change over time.

It might take several clock cycles before a single computer instruction has been fully processed. In one architecture, the computer instruction stays in place while over multiple steps the logic examines its contents—addresses, data, etc.—and executes it. In another, the computer instruction can be passed down through a series of registers in a pipeline, like a factory assembly line. At each stage in its progression through the pipeline, additional work is done to complete the execution of the computer instruction. In either case, the finite state machine keeps on chugging along like a worker bee tending the queen bee.

The pipeline arrangement can give the impression that one instruction takes one clock cycle. This is a bit of an illusion, since multiple instructions are resident simultaneously in the several stages of the pipeline, yet one result is completed every cycle. This is analogous to Henry Ford's assembly line: there might be 100 or 200 cars in work at any moment, but one pops out every hour, giving the superficial impression that it only takes an hour to build a car.

Microcode is a variation on all this. Instead of calculating the outputs in each cycle, the logic simply looks up what those outputs should be, drawing them from a special-purpose memory that holds them. Want action A? Take the memory word that matches it and use it to supply the desired outputs. To create the memory code, jam the correct bits in the correct locations. Today the main reason microcode is out of favor is because memory is slower than logic. If that should change when some new technology emerges, you might see microcode again, since it then would be faster.

Superscalar processors use multiple pipelines in parallel, with logic used to dispatch a computer instruction to the appropriate pipeline. One—or multiple— pipelines might handle multiplication, for example, while others handle memory access. As instructions exit the pipeline, the results need to be put back together again in the appropriate sequence so that you get the right answer whether there are parallel pipelines or not.

But as one commenter said, the study of processor architecture spans many books and is deep. I support the recommendation that you get a good book. I would recommend Heuring, Vincent P., Harry Frederick Jordan, and Miles Murdocca. Computer systems design and architecture. Addison-Wesley, 1997. This is a clearly written introduction to computer architecture and gives detailed explanations of everything you're asking about.

After that try Shen, John Paul, and Mikko H. Lipasti. Modern processor design: fundamentals of superscalar processors. Waveland Press, 2013. It's not as well written, but it covers a wide range of techniques used in modern processors.

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  • \$\begingroup\$ Thanks, this helped a lot. \$\endgroup\$ Commented Jun 3, 2022 at 16:54
  • \$\begingroup\$ The book by Heuring et al. explains how to design the circuits to do the needed steps. Very interesting and illuminating. \$\endgroup\$ Commented Jun 3, 2022 at 19:35
  • \$\begingroup\$ It might take several clock cycles for some instructions today with ALU's, yet primitive CPU's were like RISC machines with single clock cycle per instruction and defined by Turing in his time in R&D. Read the Turing Machine architecture. Also an ARM processor executes an instruction in one clock cycle, it is a RISC, a reduced instruction set processor, like telephony call-routing computers. The PC is a CISC processor, more complicated instruction set, yet more secure than the RISC. Do you agree? \$\endgroup\$ Commented Jun 4, 2022 at 5:05
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Primitive CPUs were like RISC machines with a single clock cycle per instruction and were defined by Turing in his time in R&D. Read the Turing Machine architecture. Also, an ARM processor executes an instruction in one clock cycle, it is a RISC, a reduced instruction set processor, like telephony call-routing computers. The PC is a CISC processor, a more complicated instruction set, yet more secure than the RISC.

Don't you agree?

When using microcode in PALM portables (Put All Logic in Microcode) the Logic was once done all in RTL or TTL or 3 Gate Arrays for the Palm for single instructions and let CPU do the >1clock cycle do the rest.

That was the distinction to answer your question.

The Abacus had human pre-processors. ;)

The 1st NASA flight computer used all rad-hardened discrete logic to fetch instructions and execute them. The bigger the junction, the higher levels of Gamma rays could be tolerated with the contamination that could cause a partial discharge voltage breakdown or inject a false clock edge and fault code. But could be reset with specific instructions to clear that error. It worked, even with errors that did occur.

Also review https://stackoverflow.com/questions/2782014/turing-machine-vs-von-neuman-machine

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  • \$\begingroup\$ I disagree. Primitive CPUs were usually many clock cycles per instruction since you can't get much done in one clock cycle. You can look at early mainframes such as EDSAC or the IBM 701, or early microprocessors such as the Intel 4004 or 8008 or the MOS 6502. RISC wasn't until later. \$\endgroup\$ Commented Jan 1, 2023 at 1:41

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