In the OPA365 specification sheet there is this example circuit where they add a RC filter between a unity buffer and input of an ADC. My understanding of the purpose of this \$ 100 \,\Omega - 1\operatorname{nF} \$ RC filter is to anti-alias the signal coming out of the buffer - by filtering out any components higher than 250kHz before it enters a 250kSPS ADC. But when I calculate the cutoff frequency with the chosen RC values, I get:

$$ f_c = \frac{1}{2\pi RC} = \frac{1}{2\pi *100*(1*10^{-9})} \approx 1.6 \,\operatorname{MHz} $$

1.6 MHz is more than six times larger than 250kHz! This RC filter is NOT anti-aliasing the signal into the ADC. Even if I take account of the open loop output impedance (\$ 30\,\Omega\$), I still end up having a cutoff frequency of \$ 1.2\operatorname{MHz} \$. Also according the the Nyquist theorem, I should set my cutoff frequency to at least half of the ADC sampling rate, or 125kHz, by setting my RC values to be 12-13 times larger than what TI chooses for this example circuit.

So why and how is this \$ 100 \,\Omega - 1\operatorname{nF} \$ pair chosen?

enter image description here

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    \$\begingroup\$ A lot of times people are just doing ad-hoc filtering on ADC's. For example, if you sample battery voltage once per minute, does that mean you need a low pass filter with to cutoff everything above 1/120 Hz? If the signal does not have bandwidth in the region that would be aliased, it may not be necessary to filter it before sampling. Or, if you do filter it, the filter can be tailored to greatly attenuate noise from known sources. \$\endgroup\$
    – user57037
    Jun 3, 2022 at 3:12
  • \$\begingroup\$ Keep in mind that the series resistance between the op-amp and ADC creates a DC error because the ADC input has some impedance and/or leakage current. So, if you do tune the filter, don't get carried away making the R super large. Or at least investigate what the input resistance and leakage current are so you can make a smart choice of series resistor. \$\endgroup\$
    – user57037
    Jun 3, 2022 at 3:15
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    \$\begingroup\$ Start reading about where Figure 40 resides in the ADC datasheet. Note how long it takes to charge up the ADC input capacitance: 4.5 cycles or 750 ns. \$\endgroup\$
    – jonk
    Jun 3, 2022 at 3:23
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    \$\begingroup\$ This isn't an anti aliasing filter, it is a charge bucket filter. It helps provide instantaneous current to a capacitive ADC. \$\endgroup\$ Jun 3, 2022 at 3:30
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    \$\begingroup\$ The charge bucket filter performs a different role than the anti-aliasing filter. They are typically implemented separately. This is because the charge bucket is meant to supply the quick current needed between acquisitions. The anti-aliasing is to prevent aliasing. The charge bucket filter needs to have cap with very little ESR +E ESL to ADC input. Aliasing is more lenient \$\endgroup\$ Jun 3, 2022 at 4:59

3 Answers 3


It is clear in the question that it is already known that the RC has nothing to do with anti-aliasing for the sampling frequency mentioned. From the ADC datasheet we can get an equivalent input circuit as follows:

enter image description here

Note that the switch also models the "On resistance". You can understand that the first capacitor, which is much larger that the second one, works like a large bucket quickly filling a small cup, through the switch resistance:

enter image description here

So, it is not related to "frequencies the cause instability to the charging capacitor", but to quickly charging the sample-and-hold capacitor.

So why and how is this \$ 100 \,\Omega - 1\operatorname{nF} \$ pair chosen?

Here is a nice reference from TI about "Charge Bucket Filter Design". But in the ADC datasheet, this information is to be found:

enter image description here

Ideally the resistor would be zero (but it may be a problem for the opamp) and the capacitor should be large enough so the amount of charge it looses to charge the ADC capacitance is small enough to avoid further conversion errors within the sampling frequency (and parasitic inductance and resistance could be a problem too for the large capacitors).


It is not for anti-alias filtering.

When the ADC performs a conversion, it charges a capacitor to the input voltage and charging the capacitor takes a surge of current. So at 250 ksps, the ADC input causes current surges to the op-amp output at a rate of 250 kHz.

Many op-amps can't drive that kind of load and can become unstable. The RC filter is there to isolate the ADC input from the op-amp output.

The RC filter removes a lot of high frequency content of the surges so load for the op-amp output is easier for it to handle.

The capacitor provides a low enough impedance to the ADC input at high frequencies and can provide the current to charge up the ADC sampling capacitor quickly, in the time it needs to be charged during the sampling phase.

The resistor provides a high enough impedance to the op-amp so the capacitance on output and the ADC sampling capacitor being switched at the sampling rate does not make it unstable.

That is why the ADC datasheet says that RC values are application specific and may need adjustments. The values depend on ADC sampling rate and which op-amp is driving the ADC input.

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    \$\begingroup\$ No, it would be better for many reasons. First of all, setting first order filter RC cutoff to 250 kHz will not attenuate enough frequencies above 250 kHz. It would make more sense to filter the frequencies away enough before buffering to DAC, as this op-amp is very fast and powerful (50 MHz, tens of milliaps output to drive capacitive load quickly). So it makes no sense to allow op-amp to buffer 50 MHz signals with large current into 250 kHz RC filter, it should just be used to drive the ADC input strongly with already bandlimited signal. \$\endgroup\$
    – Justme
    Jun 3, 2022 at 14:45

This is not really a filter but a matching network between the output of the op-amp and the switched capacitor input of the ADC. Its purpose is twofold:

  1. to shield the op-amp from the disturbances of the ADC input sampling transients,

  2. to provide a charge reservoir to refill the ADC input sampling capacitors,

  3. to isolate the channels from each other as the input multiplexer scans them, leaking charge from previous channel to the next one in the scan sequence.

ADC input sampling and multiplexing switching produces very fast transients - they are more in the frequency realm of fast digital edges than what we'd think of as "analog" signals. Those transients are often orders of magnitude shorter than the sampling period of the ADC. E.g. a 100ks/s ADC that samples every 10us and has a 1us sampling gate time, might have transients that last only tens of ns. The more modern the ADC, the faster the transients, as a rule of thumb.

Most affordable op-amps that drive high-resolution ADCs don't nearly have enough bandwidth (or low enough noise) to deal with those transients directly. The op-amp's feedback loop must be thus shielded from the transient, so it doesn't get disturbed and then take "eons" to recover. The sampling capacitors must be also provided a secondary, much faster charge source than the op-amp's output can provide.

There are three time "constants" we need to keep in mind here:

  1. the sampling period - this determines the Nyquist frequency and drives the design of the antialiasing filter,

  2. the sample gate time - the time the sampling capacitor actually samples the input - this determines how quickly the input voltage must settle to maintain full accuracy,

  3. the sampling and multiplexing transient - the time it takes for the impedance stabilization of the CMOS switches used to sample and multiplex the ADC input, as well as the time it takes to precharge the sampling capacitor to the rough neighborhood of the input voltage.

As a rule of thumb, each subsequent time in this list is at least an order of magnitude shorter than the preceding one.

As for choosing the values: absent very accurate models of the parasitics involved, it takes experimentation to select appropriate values. Often there may be two or three disparate combinations of parts that yield equally good performance, e.g. 1nF+20R or 1uF+50R. It is also the case that more such varied combinations work with a faster op-amp, but the slower op-amps won't be able to cope with the "fastest" combinations. E.g. an op-amp substitution may make the 1nF network useless, whereas the 1uF network works for both.


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