If you really want to get this 10W you need a drive stage between the output stage and voltage amplifier stage (Q3).
You could try to use this topology:

simulate this circuit – Schematic created using CircuitLab
And ballpark calculations will look like this:
Assuming \$P = 10W\$ for \$R_L = 8Ω\$
This means that \$V_{L_{max}} = \sqrt{2*P*R_L} = \sqrt{2* 10W * 8Ω} ≈ 12.7V\:\: [peak]\$
And the load current:
\$ I_{L_{max}} = \frac{V_{L_{max}}}{R_L} = 1.6A \:\:[peak] \$
For good thermal stability of an output stage, I decided to choose:
\$R8 = R9 = \frac{V_{BE}}{ I_{L_{max}}} ≈ \frac{0.8V}{1.6A} ≈ 0.47Ω \:\:[2W]\$
The output stage quiescent current (\$I_Q\$) can be set via a pot (R12) connected across VBE multiplier \$Q_8\$. And this current we need to be set on the lab bench.
\$I_Q = (2...5)\% I_{L_{max}} ≈ 50mA\$
Now if we assume \$\beta_7 = 20\$ for \$Q_6\$ and \$Q_7\$ and \$\beta_4 = 100\$ for \$Q_4\$ and \$Q_5\$ we can select \$I_{C3}\$ quiescent current.
\$ I_{C3} ≥ (5..20) * \frac{ I_{L_{max}}}{\beta_7 * \beta_4} = (5..20)* \frac{1.6A}{20 * 100}≈ 5mA\$
Due to negative feedback action, we know that the DC output voltage will be close to 0V. Thus, we can select \$R_{10}\$ and \$R_{11}\$.
\$ R_{10}+R_{11} ≈ \frac{Vcc}{I_{C3}} = \frac{15V}{5mA} = 3kΩ\$
\$R_{10} = R_{11} = \frac{3kΩ}{2} = 1.5kΩ\$
The input stage quiescent current we can find in a similar fashion, knowing Q3 DC current.
\$I_{C1} = 10 * \frac{I_{C3}}{\beta_{min}} = 10 * \frac{5mA}{100} = 0.5mA\$
\$R_2 = \frac{V_{BE3}}{I_{C1}} = \frac{0.7V}{0.5mA} ≈ 1.3kΩ\$
\$R_1 = \frac{Vcc - Vbe}{2*I_{C1}} = \frac{15V - 0.6V}{1mA} ≈ 13kΩ\$
Notice that \$R_3\$ determines the amplifier input resistance. And to reduce the "DC offset" \$R_5\$ should be equal to \$R_3\$
\$R_3 = R_5 = 10kΩ\$
\$R_4\$ will set the amplifier voltage gain.
\$R_4 = \frac{10kΩ}{10} ≈ 1kΩ\$ (gain equals to 10)
Input capacitor and C2 w set the low-frequency corner frequency
\$C_2 = \frac{0.16}{R_4 * F_C} = \frac{0.16}{1kΩ * 10Hz} ≈ 22μF\$
\$C1 = \frac{0.16}{R_3*F_C} = \frac{0.16}{10kΩ*10Hz} ≈ 2.2μF\$
\$C_C = 10pF\$ but we select the correct size of this capacitor by testing it on the test bench.
The bootstrapping capacitor:
Bootstrap in power amplifier
\$C_3 = \frac{0.16}{R_{10}||R_{11} * F_C} ≈ 22μF \$
The average power dissipation in the output stage transistor (in Q6 and Q7) is equal to:
\$P_{D} ≈ 0.1*\frac{V_{CC}^2}{RL} = 0.1*\frac{15V^2}{8Ω} ≈ 2.8W\$ plus a DC current looses \$I_Q*V_{CC} = 50mA*15V = 0.75W\$
And the peak power dissipation \$P = \frac{15V^2}{4*8Ω} = 7W \$
The power in \$Q_4\$ and \$Q_5\$ is \$\frac{P_D}{\beta_7}\$. And the power dissipation in \$ Q_3\$ is \$5mA * 15V = 0.075W\$
And \$Q_8\$ (Vbe multiplier transistor) should be thermally connected with \$Q_4\$.
Now it is time to test the circuit and tweak the component values if needed. To meet the requirements.