I'm currently doing a project, and I can't find the reason when my result is XXXXXX which is error. The code run smoothly when I test, but when I want to see the result, it comes out something I can't understand.
Here's my code :
module cu_dpu_combine(clk,start,X,Y,W,Z,result);
input clk, start ;
input [7:0] X,Y,W,Z;
output [13:0] result ;
wire Sel_1,Sel_0, ld ;
wire [1:0] op;
cu u1(clk,start,Sel_1,Sel_0,ld,op);
dpu u2(X,Y,W,Z,clk,ld,op,Sel_0,Sel_1,result);
endmodule
module cu(clk,start,Sel_1,Sel_0,ld,op);
input clk, start ;
output Sel_1,Sel_0 ;
output ld ;
output [1:0] op;
reg Sel_1 , Sel_0;
reg ld;
reg [1:0] op;
reg [3:0] next_state ;
reg [3:0] present_state;
parameter [3:0] s0=0, s1=1, s2=2, s3=3, s4=4, s5=5, s6=6, s7=7, s8=8, s9=9, s10=10 , s11=11;
// next state logic
always@(present_state, start)
begin
case(present_state)
s0: if(start == 0)
next_state = s0 ;
else
next_state = s1 ;
s1: next_state = s2 ; //result = X
s2: next_state = s3 ; //result = result + X
s3: next_state = s4 ; //result = result - Y
s4: next_state = s5 ; //result = result - Y
s5: next_state = s6 ; //result = result + W
s6: next_state = s7 ; //result = result + W
s7: next_state = s8 ; //result = result + W
s8: next_state = s9 ; //result = result + W
s9: next_state = s10 ; //result = result - Z
s10: next_state = s11 ; //result = result - Z
s11: next_state = s0 ; //result = result - Z
default : next_state = s0;
endcase
end
///////////////////////////////
//the D flip-flops (register)
///////////////////////////////
always@(posedge clk)
begin
present_state <= next_state;
end
///////////////////////////////
///////////////////////////////
//output logic
///////////////////////////////
always @(present_state)
begin
case(present_state)
s0: {Sel_1,Sel_0,ld,op} = 5'b00000 ; //initial condition
s1: {Sel_1,Sel_0,ld,op} = 5'b00110 ; //form X
s2: {Sel_1,Sel_0,ld,op} = 5'b00100 ; //add X
s3: {Sel_1,Sel_0,ld,op} = 5'b01101 ; //subtract Y
s4: {Sel_1,Sel_0,ld,op} = 5'b01101 ; //subtract Y
s5: {Sel_1,Sel_0,ld,op} = 5'b10100 ; //add W
s6: {Sel_1,Sel_0,ld,op} = 5'b10100 ; //add W
s7: {Sel_1,Sel_0,ld,op} = 5'b10100 ; //add W
s8: {Sel_1,Sel_0,ld,op} = 5'b10100 ; //add W
s9: {Sel_1,Sel_0,ld,op} = 5'b11101 ; //subtract Z
s10: {Sel_1,Sel_0,ld,op} = 5'b11101 ; //subtract Z
s11: {Sel_1,Sel_0,ld,op} = 5'b11101 ; //subtract Z
default : {Sel_1,Sel_0,ld,op} = 5'b00000;
endcase
end
endmodule
module dpu(X,Y,W,Z,clk,ld,op,Sel_0,Sel_1,result);
input [7:0] X,Y,W,Z;
input Sel_0,Sel_1;
input clk;
input ld;
input [1:0] op;
output [13:0] result;
reg [13:0] result; //14bit
reg [13:0] ar_out ; //14bit
wire [13:0] mux_out ; //8bit
//selection for output of multiplexer
assign mux_out = (Sel_1==1) ? ((Sel_0==0) ? W : Z) : ((Sel_0==0) ? X : Y);
//alu
always @(*)
begin
case(op)
0: ar_out = mux_out + result ;
1: ar_out = result - mux_out ;
2: ar_out = mux_out ;
3: ar_out = 8'b0 ;
endcase
end
//register
always @ (posedge clk)
begin
if(ld)
result <= ar_out ;
end
endmodule
//2X-2Y+4W-3Z
Here's my testbench code.
module testbench;
// Inputs
reg clk;
reg start;
reg [7:0] X;
reg [7:0] Y;
reg [7:0] W;
reg [7:0] Z;
// Outputs
wire [13:0] result;
// Instantiate the Unit Under Test (UUT)
cu_dpu_combine uut (
.clk(clk),
.start(start),
.X(X),
.Y(Y),
.W(W),
.Z(Z),
.result(result)
);
initial begin
// Initialize Inputs
clk = 0;
start = 0;
X = 0;
Y = 0;
W = 0;
Z = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
start=0 ;
X =64 ; Y=64 ; W =64 ; Z= 64 ;
repeat(2) @(posedge clk) ;
start=1 ; @(posedge clk) ;
start = 0 ;
repeat(12) @(posedge clk) ;
X =128 ; Y=128 ; W =128 ; Z= 128 ;
repeat(1) @(posedge clk) ;
start=1 ; @(posedge clk) ;
start = 0 ;
repeat(12) @(posedge clk) ;
X =255 ; Y=255 ; W =255 ; Z= 255 ;
repeat(1) @(posedge clk) ;
start=1 ; @(posedge clk) ;
start = 0 ;
repeat(12) @(posedge clk) ;
$stop ;
end
endmodule
