Somewhere around the end of transmitting a byte in Master Transmit mode the following is observed(SCL - yellow, SDA - blue).
I am mainly interested in
- What is the tiny pulse on the right? STOP? START? ACK? glitch?
But those clarifications would also help:
- Is the non-square clock a reason for concern?
- What is the left pulse? It's too early for a STOP so I guess it's a data bit
1. But is it usual to keep the level during SCL==high?
- The master is configured for Normal mode 100kBps but the frequency of the clock it emits is 87.4kHz(clock stretching is enabled but not observed). Is that normal?