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Since my previous question I've reduced the clock to 10kHz and am now trying to interpret what the pulses mean.

My reading of the image is 0b00110010 being transmitted. Which is exactly what I would have expected from this code.

const uint8_t address = 0x49 << 1;
const uint8_t tempr_reg = 0x00;
static char buf[12];
// Read 2 bytes, MSB first.
HAL_I2C_Master_Transmit(&hi2c1, address, &tempr_reg, sizeof(tempr_reg), HAL_MAX_DELAY);
HAL_I2C_Master_Receive(&hi2c1, address, buf, 2, HAL_MAX_DELAY);

enter image description here

Here is a zoom-in of the pulse. enter image description here

Why is it 9 bits later instead of 8? Is the SDA low (between the red line and the SDA pulse) a slave ACK? If so, who holds SDA low during CLK==high after the 8th bit? Yet the pulse occurs after the ACK - I'm really confused.

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    \$\begingroup\$ do yourself a favour and get a cheapy logic analyser off of ebays. Usually less than $10 usd. Use Sigrok to run it. Decodes I2C and other protocols for you. You wont regret buying one (or two) \$\endgroup\$
    – Kartman
    Jun 9, 2022 at 15:05
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    \$\begingroup\$ @Kartman it even features firmware for my OS! \$\endgroup\$
    – Vorac
    Jun 9, 2022 at 15:17
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    \$\begingroup\$ the oscilloscope screen would be easier to read if the two traces do not overlap \$\endgroup\$
    – jsotola
    Jun 9, 2022 at 15:33

2 Answers 2

Reset to default
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Why is it 9 bits later instead of 8? Is the SDA low (between the red line and the SDA pulse) a slave ACK?

Yes. Check the first half of this figure, from the I2C standard:

enter image description here

If so, who holds SDA low during CLK high after the 8th bit?

The explanation follows the figure in the same page of document:

enter image description here

Edit following the comment below:

enter image description here

The device holding the SDA down switches over twice controller -> receiver -> controller during the ACK procedure. I agree with @Justme that the spike you see is caused by the receiver releasing the SDA line at the end of the ACK.

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    \$\begingroup\$ I almost got it. "the SDA low (between the red line and the SDA pulse)" - the 9th bit - is a slave ACK. But from the accepted answer to the linked question "The short pulse occurs after the 8th data bit and just before the ACK.". How come it occurs after 9 bits here? \$\endgroup\$
    – Vorac
    Jun 9, 2022 at 13:16
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    \$\begingroup\$ I've tried to improve the answer to address this point which was still unclear in the text. \$\endgroup\$
    – devnull
    Jun 9, 2022 at 13:25
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    \$\begingroup\$ Still not consistent with "The short pulse occurs after the 8th data bit and just before the ACK." but the picture is so awesome! \$\endgroup\$
    – Vorac
    Jun 9, 2022 at 13:32
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    \$\begingroup\$ Indeed. It is clearly behaving differently from the previous post. My first attempt to explain would be that now the measurements use \$\approx 1/10\$ of the CLK. Now it is clear that the spike occur after the 9th clock pulse, after the second switchover (not the first one). If the HW people managed to replace the resistor, you could update the measurement with the higher clock freq. (of the whole frame). \$\endgroup\$
    – devnull
    Jun 9, 2022 at 13:35
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That is exactly how a byte transmission with ACK can look like, but not necessarily will look like.

The short spike is because slave is releasing the SDA to go high after being done transmitting a low ACK bit, and then the master will start pulling the SDA low to transmit a zero bit.

Depending on slave and master timings, the spike could be longer, or non-existent, if master starts pulling low before slave releases the bus.

Remember that during SCL high nobody is allowed to change data because it would signal start or stop condition, and data is allowed to change only during SCL low.

So that's what devices do. They set or release the data pin after a falling edge so the data is stable to clock in at next rising edge.

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